Satoru HANZAWA


Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device
Satoru HANZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/08/01
Vol. E94-C  No. 8  pp. 1302-1310
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
content addressable memoryCAMparallel searchphase-change deviceone-hot codingnonvolatile memory
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Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation
Riichiro TAKEMURA Kiyoo ITOH Tomonori SEKIGUCHI Satoru AKIYAMA Satoru HANZAWA Kazuhiko KAJIGAYA Takayuki KAWAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 758-764
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
twin-cell DRAM arraywrite timelow voltage RAMretention timeand plate-driven cell
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A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory
Satoru HANZAWA Takeshi SAKATA Tomonori SEKIGUCHI Hideyuki MATSUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/09/01
Vol. E86-C  No. 9  pp. 1886-1893
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
emerging memoryMISS tunnel-diodehierarchical bit-line structuretwin dummy-cell
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A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
Satoru HANZAWA Hiromasa NODA Takeshi SAKATA Osamu NAGASHIMA Sadayuki MORITA Masanori ISODA Michiyo SUZUKI Sadayuki OHKUMA Kyoko MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1625-1633
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
clock-recovery circuittiming adjusterdelay lineDDR SDRAM
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