Sadayuki OHKUMA


A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
Satoru HANZAWA Hiromasa NODA Takeshi SAKATA Osamu NAGASHIMA Sadayuki MORITA Masanori ISODA Michiyo SUZUKI Sadayuki OHKUMA Kyoko MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1625-1633
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
clock-recovery circuittiming adjusterdelay lineDDR SDRAM
 Summary | Full Text:PDF

A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology
Sadayuki OHKUMA Hiroshi ICHIKAWA Seigo YUKUTAKE Hitoshi ENDO Shuichi KUBOUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 763-766
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
synchronous SRAMlate writeshort cycle timeregisler
 Summary | Full Text:PDF