Sadami TAKEOKA


On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis
Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1671-1677
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
path delay faultuntestable pathpotentially testable pathfault efficiency
 Summary | Full Text:PDF(252.5KB)

Evaluation of Delay Testing Based on Path Selection
Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA Shinichi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3208-3210
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
delay testingpath delay faultpath selectionuntestable path
 Summary | Full Text:PDF(162.4KB)

A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis
Akira MOTOHARA Sadami TAKEOKA Mitsuyasu OHTA Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1436-1442
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design for Testability
Keyword: 
design for testabilitypartial scan designregister-transfer levelautomatic test-pattern generationESDA
 Summary | Full Text:PDF(732.9KB)