Ryuta KAWANO


The Study of Low-latency On-chip Topology using Multiple Core Links
Ryuta KAWANO Ikki FUJIWARA Hiroki MATSUTANI Hideharu AMANO Michihiro KOIBUCHI 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2014/03/01
Vol. J97-D  No. 3  pp. 601-613
Type of Manuscript:  PAPER
Category: 
Keyword: 
Network-on-Chip (NoC)topologyinterconnection networks
 Summary | Full Text(in Japanese):PDF(1.6MB)