Ryuta KAWANO


A Layout-Oriented Routing Method for Low-Latency HPC Networks
Ryuta KAWANO Hiroshi NAKAHARA Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   
Publication Date: 2017/12/01
Vol. E100-D  No. 12  pp. 2796-2807
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Interconnection networks
Keyword: 
high performance computingnetwork topologyinterconnection networks
 Summary | Full Text:PDF(1.5MB)

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator
Yusuke MATSUSHITA Hayate OKUHARA Koichiro MASUYAMA Yu FUJITA Ryuta KAWANO Hideharu AMANO 
Publication:   
Publication Date: 2017/12/01
Vol. E100-D  No. 12  pp. 2828-2836
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
CGRAbody biaspower reductioncool mega array
 Summary | Full Text:PDF(1.1MB)

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing
Ryuta KAWANO Hiroshi NAKAHARA Seiichi TADE Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1798-1806
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
deadlock-free routinghigh performance computingtime complexity
 Summary | Full Text:PDF(988.8KB)