Ryuji YOSHIMURA


Watch-Dog Circuit for Quality Guarantee with Subthreshold MOSFET Current
Tetsuya HIROSE Ryuji YOSHIMURA Toru IDO Toshimasa MATSUOKA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1910-1914
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
CMOSsubthreshold currentultra-low-powertemperature dependence
 Summary | Full Text:PDF

Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface
Boon-Keat TAN Ryuji YOSHIMURA Toshimasa MATSUOKA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11  pp. 1521-1527
Type of Manuscript:  Special Section PAPER (Special Issue on Function Integrated Information Systems)
Category: 
Keyword: 
CDMA busparallel processinginterconnection topologyrouting flexibilityfault tolerant
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A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing
Boon-Keat TAN Ryuji YOSHIMURA Toshimasa MATSUOKA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 741-747
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
DPAADSPparallel processinginterconnection topologyrouting flexibility
 Summary | Full Text:PDF

A Reconfigurable Digital Signal Processor
Boon Keat TAN Toru OGAWA Ryuji YOSHIMURA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1424-1430
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DSP processorreconfigurableflexibleprocessors arrayfault-tolerantASICdigital signal processingRISC
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