Ryo KISHIDA

Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation
Satoshi SEKINE Tatsuji MATSUURA Ryo KISHIDA Akira HYOGO 
Publication:   
Publication Date: 2021/02/01
Vol. E104-A  No. 2  pp. 516-524
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog-to-digital converter (ADC), digital-to-analog converter (DAC), successive approximation register ADC (SAR-ADC), C-C SAR-ADC, digital correction, γ-estimation, 
 Summary | Full Text:PDF
Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model
Takuya KOMAWAKI Michitarou YABUUCHI Ryo KISHIDA Jun FURUTA Takashi MATSUMOTO Kazutoshi KOBAYASHI 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2758-2763
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Random Telegraph Noise, reliability, Verilog-AMS, 
 Summary | Full Text:PDF
Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs
Michitarou YABUUCHI Ryo KISHIDA Kazutoshi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2367-2372
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
BTI, process variation, reliability, 
 Summary | Full Text:PDF