Rong-Jyi YANG


A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
Rong-Jyi YANG Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8  pp. 1726-1730
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
DLLCDRdual loop
 Summary | Full Text:PDF

A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs
Rong-Jyi YANG Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6  pp. 1248-1252
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
Keyword: 
DLLclock generationwide rangeduty cycle correction
 Summary | Full Text:PDF