Qing DONG


Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC
Gong CHEN Yu ZHANG Qing DONG Ming-Yu LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1442-1454
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
leakage current reductionlayout dependent effectlow-power SAR-ADC
 Summary | Full Text:PDF

Structured Analog Circuit and Layout Design with Transistor Array
Bo YANG Qing DONG Jing LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2475-2486
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
transistor arraychannel decompositionstructured analog designmanufacturability
 Summary | Full Text:PDF

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming
Yu ZHANG Gong CHEN Bo YANG Jing LI Qing DONG Ming-Yu LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2487-2498
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
circuit synthesisSTIWPEchannel length modulationgeometric programming
 Summary | Full Text:PDF

Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
Qing DONG Bo YANG Jing LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3103-3110
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
placementfloorplanbuffer insertionmodule resizinggeometric programming
 Summary | Full Text:PDF