Qiang ZHOU


Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation
Junbo YU Qiang ZHOU Gang QU Jinian BIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3151-3159
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
peak temperaturerebindingreallocationbehavioral synthesis
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Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
Liangpeng GUO Yici CAI Qiang ZHOU Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/08/01
Vol. E91-A  No. 8  pp. 2084-2090
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
voltage islandlevel converterlow powerplacement
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Voltage Island Generation in Cell Based Dual-Vdd Design
Yici CAI Bin LIU Qiang ZHOU Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 267-273
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
dual-Vddlayoutplacementvoltage islandvoltage assignment
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Navigating Register Placement for Low Power Clock Network Design
Yongqiang LU Chin-Ngai SZE Xianlong HONG Qiang ZHOU Yici CAI Liang HUANG Jiang HU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3405-3411
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan and Placement
Keyword: 
clock networkstandard cellquadratic placementprescribed skew
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A Fast Delay Computation for the Hybrid Structured Clock Network
Yi ZOU Yici CAI Qiang ZHOU Xianlong HONG Sheldon X.-D. TAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7  pp. 1964-1970
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock networkssimulationanalysisdelayElmore delay
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Crosstalk and Congestion Driven Layer Assignment Algorithm
Bin LIU Yici CAI Qiang ZHOU Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/06/01
Vol. E88-A  No. 6  pp. 1565-1572
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
congestioncrosstalklayer assignmentVLSI
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