Patrick GIRARD

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
Akihiro TOMITA Xiaoqing WEN Yasuo SATO Seiji KAJIHARA Kohei MIYASE Stefan HOLST Patrick GIRARD Mohammad TEHRANIPOOR Laung-Terng WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10  pp. 2706-2718
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
at-speed scan-based logic BIST, capture power safety, masking, IR-drop, transition delay fault, long sensitized path, 
 Summary | Full Text:PDF
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
Kohei MIYASE Xiaoqing WEN Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA Patrick GIRARD Laung-Terng WANG Mohammad TEHRANIPOOR 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 2-9
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
power supply noise, test relaxation, X-filling, clock-gating, test compaction, 
 Summary | Full Text:PDF