| Nozomu TOGAWA
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X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12
pp. 3119-3127
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: scan test, test data compression, X-masking, | | Summary | Full Text:PDF | |
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A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A
No. 12
pp. 3514-3523
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: scan test, test data compression, X-masking, | | Summary | Full Text:PDF | |
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A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs Nozomu TOGAWA Koji ARA Masao YANAGISAWA Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A
No. 3
pp. 473-482
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: technology mapping, logic-block, lookup table, logic depth, | | Summary | Full Text:PDF | |
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A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A
No. 3
pp. 321-329
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: FPGA, technology mapping, layout, path delay, performance optimization, | | Summary | Full Text:PDF | |
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