IEICE Trans

Nozomu TOGAWA

A Two-Stage Hardware Trojan Detection Method Considering the Trojan Probability of Neighbor Nets Kento HASEGAWA Tomotaka INOUE Nozomu TOGAWA
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1516-1525 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: hardware Trojan, gate-level netlist, design time, neural networks, machine learning,
	Summary \| Full Text:PDF

Analysis and Acceleration of the Quadratic Knapsack Problem on an Ising Machine Matthieu PARIZY Nozomu TOGAWA
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1526-1535 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: Ising model, Ising machine, knapsack problem, visualization,
	Summary \| Full Text:PDF

An Anomalous Behavior Detection Method Utilizing Extracted Application-Specific Power Behaviors Kazunari TAKASAKI Ryoichi KIDA Nozomu TOGAWA
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1555-1565 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: power analysis, IoT device, anomalous behavior, steady-state power waveform, application-specific power waveform,
	Summary \| Full Text:PDF

An Ising Machine-Based Solver for Visiting-Route Recommendation Problems in Amusement Parks Yosuke MUKASA Tomoya WAKAIZUMI Shu TANAKA Nozomu TOGAWA
Publication: Publication Date: 2021/10/01 Vol. E104-D No. 10 pp. 1592-1600 Type of Manuscript: PAPER Category: Computer System Keyword: Ising machine, amusement park, combinatorial optimization problem, Ising model, quadratic unconstrained binary optimization,
	Summary \| Full Text:PDF

Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine Natsuhito YOSHIMURA Masashi TAWADA Shu TANAKA Junya ARAI Satoshi YAGI Hiroyuki UCHIYAMA Nozomu TOGAWA
Publication: Publication Date: 2021/04/01 Vol. E104-D No. 4 pp. 481-489 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: induced subgraph, isomorphism problem, Ising machines, Ising model, annealing machine, quadratic unconstraint binary optimization,
	Summary \| Full Text:PDF

Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations Sho KANAMARU Kazushi KAWAMURA Shu TANAKA Yoshinori TOMITA Nozomu TOGAWA
Publication: Publication Date: 2021/02/01 Vol. E104-D No. 2 pp. 226-236 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: Ising machine, Ising model, slot-placement problem, quadratic assignment problem, quadratic unconstrained binary optimization,
	Summary \| Full Text:PDF

A Capacitance Measurement Device for Running Hardware Devices and Its Evaluations Makoto NISHIZAWA Kento HASEGAWA Nozomu TOGAWA
Publication: Publication Date: 2020/09/01 Vol. E103-A No. 9 pp. 1018-1027 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: hardware security, capacitance measurement, anomalous function detection, low power,
	Summary \| Full Text:PDF

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2020/07/01 Vol. E103-D No. 7 pp. 1618-1622 Type of Manuscript: Special Section LETTER (Special Section on Information and Communication System Security) Category: Network and System Security Keyword: hardware Trojan, gate-level netlist, Trojan feature, boundary nets, hardware design,
	Summary \| Full Text:PDF

A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines Daisuke OKU Kotaro TERADA Masato HAYASHI Masanao YAMAOKA Shu TANAKA Nozomu TOGAWA
Publication: Publication Date: 2019/09/01 Vol. E102-D No. 9 pp. 1696-1706 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: CMOS annealing, Ising model, Ising computing, graph embedding, combinatorial optimization,
	Summary \| Full Text:PDF

Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone Yuri USAMI Kazuaki ISHIKAWA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2019/08/01 Vol. E102-A No. 8 pp. 953-965 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: behavior recognition, smartphone, acceleration sensor, gyro sensor, bicycle,
	Summary \| Full Text:PDF

A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions Sae IWATA Kazuaki ISHIKAWA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2019/06/01 Vol. E102-A No. 6 pp. 860-865 Type of Manuscript: LETTER Category: Intelligent Transport System Keyword: indoor/outdoor detection, sparse GPS, random forest classifier,
	Summary \| Full Text:PDF

A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests Tensei NISHIMURA Kazuaki ISHIKAWA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2019/04/01 Vol. E102-A No. 4 pp. 641-653 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: cyclic-route generation, the route length constraint, multiple routes, Point-of-Interests,
	Summary \| Full Text:PDF

Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2320-2326 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojan, detection, gate-level netlist, multi-layer neural networks, machine learning,
	Summary \| Full Text:PDF

Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning Masaru OYA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2308-2319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, steady state, signal transition, logic test,
	Summary \| Full Text:PDF

Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs Ken HAYAMIZU Nozomu TOGAWA Masao YANAGISAWA Youhua SHI
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1014-1024 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: approximate computing, energy-efficient, adder, GeAr,
	Summary \| Full Text:PDF

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element Saki TAJIMA Nozomu TOGAWA Masao YANAGISAWA Youhua SHI
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1025-1034 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: soft error, low-power, latch, C-element,
	Summary \| Full Text:PDF

A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1045-1052 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: non-volatile memory, bit-write-reducing, error-correcting codes, clustering conditions, S-bit flip conditions, S-bound graph, cluster graph, relaxed REC code,
	Summary \| Full Text:PDF

Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams Ryota ISHIKAWA Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1002-1013 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: stochastic computing, stochastic number, duplicator, bit re-arrangement, re-convergence path,
	Summary \| Full Text:PDF

A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal Sae IWATA Tomoyuki NITTA Toshinori TAKAYAMA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2018/05/01 Vol. E101-A No. 5 pp. 831-843 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: sparse GPS positioning, clustering, stayed location estimation, positioning accuracy, effective radius,
	Summary \| Full Text:PDF

Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2857-2868 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojan, gate-level netlist, Trojan-net feature, random forest, machine learning,
	Summary \| Full Text:PDF

A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2911-2924 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, multiple-bitwidth, distributed-register architecture, operation chaining, interconnection delay, floorplan,
	Summary \| Full Text:PDF

A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions Siya BAO Tomoyuki NITTA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/11/01 Vol. E100-A No. 11 pp. 2439-2450 Type of Manuscript: PAPER Category: Intelligent Transport System Keyword: pedestrian, lighting, landmark, road width, turning point, anxiety, safety, comprehensiveness,
	Summary \| Full Text:PDF

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1439-1451 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, delay variation, body biasing, interconnection delay, floorplan,
	Summary \| Full Text:PDF

A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1427-1438 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: hardware Trojan, gate-level netlist, machine learning, support vector machine (SVM), neural network (NN),
	Summary \| Full Text:PDF

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/04/01 Vol. E100-A No. 4 pp. 1015-1028 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: field-data extractor, multiplexer network, partitioning, rotator,
	Summary \| Full Text:PDF

Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching Masaru OYA Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2335-2347 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, a quantitative criterion, pattern matching, design phase,
	Summary \| Full Text:PDF

A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices Ryosuke KITAYAMA Takashi TAKENAKA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2348-2362 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: IoT, power analyzer, noise reduction, signal-averaging method, scalable measurement,
	Summary \| Full Text:PDF

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2398-2411 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: non-volatile memory, bit-write-reducing, error-correcting codes, clustering conditions, S-bit flip conditions, S-bound graph, cluster graph, REC code,
	Summary \| Full Text:PDF

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1294-1310 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan,
	Summary \| Full Text:PDF

A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1278-1293 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, process variation, interconnection delay, distributed-register architecture, scenario,
	Summary \| Full Text:PDF

Bi-Partitioning Based Multiplexer Network for Field-Data Extractors Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1410-1414 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: multiplexer network, partitioning, field-data extractor,
	Summary \| Full Text:PDF

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory Masashi TAWADA Shinji KIMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2494-2504 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: non-volatile memory, bit-write reduction, energy reduction, write-reduction code, error-correcting code,
	Summary \| Full Text:PDF

Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures Huiqian JIANG Mika FUJISHIRO Hirokazu KODERA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2547-2555 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: Camellia, side-channel attack, scan-based attack, design-for-test, scan chain, scan signature,
	Summary \| Full Text:PDF

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2484-2493 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: non-volatile memory, maximum-writing bits, error-correcting codes, Doughnut code, code expansion,
	Summary \| Full Text:PDF

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists Masaru OYA Youhua SHI Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Satoshi GOTO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2537-2546 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: hardware Trojans, golden-IC free, classification, identification, gate-level netlist,
	Summary \| Full Text:PDF

A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1366-1375 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, RDR architecture, interconnection delay, operation chaining, floorplan,
	Summary \| Full Text:PDF

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1376-1391 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, energy-optimization, interconnection delay, multiple clock domains,
	Summary \| Full Text:PDF

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead Shinnosuke YOSHIDA Youhua SHI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1406-1418 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: timing-error prediction, robust design, delay variation, overclocking,
	Summary \| Full Text:PDF

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1392-1405 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis (HLS), FPGA, floorplan, interconnection delay, MUX,
	Summary \| Full Text:PDF

Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures Mika FUJISHIRO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2434-2442 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: LED, light encryption device, side-channel attacks, scan chain, scan-based attack,
	Summary \| Full Text:PDF

Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures Mika FUJISHIRO Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/07/01 Vol. E97-A No. 7 pp. 1444-1451 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: Trivium, side-channel attacks, scan chain, scan-based attack,
	Summary \| Full Text:PDF

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages Shin-ya ABE Youhua SHI Kimiyoshi USAMI Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2597-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, interconnection delay, energy-optimization, dynamic multiple supply voltages,
	Summary \| Full Text:PDF

A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1283-1292 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: cache simulation, optimaize cache memory, multicore cache,
	Summary \| Full Text:PDF

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/01/01 Vol. E96-A No. 1 pp. 312-321 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, RDR, thermal-aware, hot spots, interconnect delays,
	Summary \| Full Text:PDF

Scan-Based Attack on AES through Round Registers and Its Countermeasure Youhua SHI Nozomu TOGAWA Masao YANAGISAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2338-2346 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: scan-based side channel attack, crypto implementation, security, testability,
	Summary \| Full Text:PDF

A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores Seungju LEE Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/09/01 Vol. E95-A No. 9 pp. 1538-1549 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: network-on-chip (NoC), hybrid NoC algorithm, hierarchical NoC, busmesh NoC (BMNoC),
	Summary \| Full Text:PDF

Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2482-2489 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power supply noise, power distribution network, signal integrity, circuit simulation,
	Summary \| Full Text:PDF

Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 pp. 1082-1090 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power supply noise, power distribution networks, signal integrity, circuit simulation,
	Summary \| Full Text:PDF

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures Ryuta NARA Kei SATOH Masao YANAGISAWA Tatsuo OHTSUKI Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2481-2489 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: scan-based side-channel attack, scan path, testability, cryptosystem, RSA, security,
	Summary \| Full Text:PDF

A Scan-Based Attack Based on Discriminators for AES Cryptosystems Ryuta NARA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3229-3237 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: scan-based attack, side-channel attack, scan chain, testability, security, cryptography, AES,
	Summary \| Full Text:PDF

A Two-Level Cache Design Space Exploration System for Embedded Applications Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3238-3247 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: two-level cache, L1/L2, cache optimization, design space exploration, cache simulation, embedded system,
	Summary \| Full Text:PDF

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures Akira OHCHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3169-3179 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, floorplan, distributed-register architecture, generalized distributed-register architecture, local register, local controller,
	Summary \| Full Text:PDF

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3119-3127 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: scan test, test data compression, X-masking,
	Summary \| Full Text:PDF

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2ⁿ) Kazuyuki TANIMURA Ryuta NARA Shunitsu KOHARA Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2304-2317 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: elliptic curve cryptography, dual-radix, modular multiplication, Montgomery multiplication, scalability, unified,
	Summary \| Full Text:PDF

An L1 Cache Design Space Exploration System for Embedded Applications Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-A No. 6 pp. 1442-1453 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: cache, cache optimization, design space exploration, cache simulation, embedded system,
	Summary \| Full Text:PDF

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3514-3523 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: scan test, test data compression, X-masking,
	Summary \| Full Text:PDF

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1054-1061 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low-density parity-check code, message-passing algorithm, intermediate message compression technique, clock gated shift register for intermediate message,
	Summary \| Full Text:PDF

A Secure Test Technique for Pipelined Advanced Encryption Standard Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 776-780 Type of Manuscript: Special Section LETTER (Special Section on Test and Verification of VLSIs) Category: Keyword: scan test, security, test quality,
	Summary \| Full Text:PDF

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3602-3612 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: low-density parity-check codes, parallel LDPC decoder architecture, message-passing algorithm, FIFO-based buffering,
	Summary \| Full Text:PDF

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 969-978 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low-density parity-check codes, partially-parallel LDPC decoder, message-passing algorithm, FPGA,
	Summary \| Full Text:PDF

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains Youhua SHI Nozomu TOGAWA Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 996-1004 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: test data compression, test channels, scan test,
	Summary \| Full Text:PDF

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 243-249 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: System LSIs and Microprocessors Keyword: elliptic curve cryptosystem, Montgmery multiplier, public-key cryptosystem, LSI design,
	Summary \| Full Text:PDF

Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1526-1537 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Adaptive Signal Processing Keyword: dynamic reconfigurable system, adaptive FEC, Reed-Solomon code with interleaving,
	Summary \| Full Text:PDF

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1340-1349 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Programmable Logic, VLSI, CAD and Layout Keyword: processor synthesis, instruction set synthesis, packed SIMD-type functional unit, packed SIMD-type instruction, hardware/software cosynthesis,
	Summary \| Full Text:PDF

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis Hideki KAWAZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 876-884 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: processor synthesis, packed SIMD type operation, hardware/software partitioning, hardware/software cosynthesis, sub-operation parallelism,
	Summary \| Full Text:PDF

FPGA-Based Reconfigurable Adaptive FEC Kazunori SHIMIZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3036-3046 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: dynamic reconfigurable system, adaptive FEC, FPGA, Reed Solomon codes,
	Summary \| Full Text:PDF

High-Level Power Optimization Based on Thread Partitioning Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3075-3082 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: high-level synthesis, low power, thread partitioning, gated clocks,
	Summary \| Full Text:PDF

A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/04/01 Vol. E87-A No. 4 pp. 830-836 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: hardware/software cosynthesis, processor synthesis, heterogeneous datapaths and heterogeneous registers,
	Summary \| Full Text:PDF

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions Nozomu TOGAWA Kyosuke KASAHARA Yuichiro MIYAOKA Jinku CHOI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3099-3109 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation Accelerator Keyword: retargetable simulator, DSP processor, packed SIMD type instruction, hardware/software cosynthesis, processor synthesis,
	Summary \| Full Text:PDF

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3218-3224 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Design Methodology Keyword: processor synthesis, packed SIMD type instruction, hardware/software partitioning, hardware/software cosynthesis, DSP processor,
	Summary \| Full Text:PDF

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories Nozomu TOGAWA Takao TOTSUKA Tatsuhiko WAKUI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/05/01 Vol. E86-A No. 5 pp. 1082-1092 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: content addressable memory, functional memory, micro processor core, hardware/software cosynthesis, hardware/software partitioning,
	Summary \| Full Text:PDF

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation Jinku CHOI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2603-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: motion estimation, block-matching, algorithm, architecture, VHDL,
	Summary \| Full Text:PDF

A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2655-2666 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High Level Synthesis Keyword: high-level synthesis, energy optimization, area/time constraints,
	Summary \| Full Text:PDF

High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 827-834 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: high-level synthesis, power estimation, gated clock, switching activity, sequential circuit,
	Summary \| Full Text:PDF

A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files Nozomu TOGAWA Takashi SAKURAI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2802-2807 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: hardware/software cosynthesis, hardware/software partitioning, digital signal processor (DSP), register file, hardware unit,
	Summary \| Full Text:PDF

Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores Nozomu TOGAWA Yoshiharu KATAOKA Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2639-2647 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: area estimation, delay estimation, hardware/software cosynthesis, digital signal processor (DSP), microprocessor,
	Summary \| Full Text:PDF

An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares Nozomu TOGAWA Masayuki IENAGA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/05/01 Vol. E84-A No. 5 pp. 1166-1176 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: high-level synthesis, control-based hardware, area/time optimization, scheduling, resource allocation,
	Summary \| Full Text:PDF

CAM Processor Synthesis Based on Behavioral Descriptions Nozomu TOGAWA Tatsuhiko WAKUI Tatsuhiko YODEN Makoto TERAJIMA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2464-2473 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design and High-level Synthesis Keyword: content addressable memory, functional memory, behavioral synthesis, behavioral description, high-level synthesis,
	Summary \| Full Text:PDF

A Hardware/Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/03/25 Vol. E83-A No. 3 pp. 442-451 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: hardware/software cosynthesis, processor core, digital signal processing, two types of register files,
	Summary \| Full Text:PDF

A Hardware/Software Cosynthesis System for Digital Signal Processor Cores Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2325-2337 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware/software cosynthesis, hardware/software partitioning, processor core, digital signal processing,
	Summary \| Full Text:PDF

A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs Nozomu TOGAWA Koji ARA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/03/25 Vol. E82-A No. 3 pp. 473-482 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: technology mapping, logic-block, lookup table, logic depth,
	Summary \| Full Text:PDF

A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration Nozomu TOGAWA Takafumi HISAKI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2563-2575 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-level Synthesis Keyword: data-flow oriented process, high-level synthesis, data-flow graph enumeration, scheduling, resource binding,
	Summary \| Full Text:PDF

A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/06/25 Vol. E81-A No. 6 pp. 1231-1241 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: scheduling, resource binding, high-level synthesis, data-flow graph, gradual time-frame reduction,
	Summary \| Full Text:PDF

An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications Nozomu TOGAWA Kayoko HAGI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 pp. 873-884 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: FPGA, engineering change, layout reconfiguration, placement and routing,
	Summary \| Full Text:PDF

Fast Scheduling and Allocation Algorithms for Entropy CODEC Katsuharu SUZUKI Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/10/25 Vol. E80-D No. 10 pp. 982-992 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High Level Synthesis Keyword: entropy CODEC, scheduling, allocation, control-flow graph,
	Summary \| Full Text:PDF

A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 pp. 1795-1806 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, transport processing, layout design, placement and routing, performance optimization, circuit delay,
	Summary \| Full Text:PDF

A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 pp. 494-505 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: FPGA, multi-FPGA system, circuit partitioning, path delay, logic-block replication,
	Summary \| Full Text:PDF

A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 321-329 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: FPGA, technology mapping, layout, path delay, performance optimization,
	Summary \| Full Text:PDF

A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 pp. 1765-1776 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, circuit partitioning, logic-block replication, network flow,
	Summary \| Full Text:PDF

Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 pp. 2028-2038 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, look up table, technology mapping, layout design, placement, global routing,
	Summary \| Full Text:PDF