IEICE Trans

Noriyuki MIURA

A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation Yoshihide KOMATSU Akinori SHINMYO Mayuko FUJITA Tsuyoshi HIRAKI Kouichi FUKUDA Noriyuki MIURA Makoto NAGATA
Publication: Publication Date: 2020/10/01 Vol. E103-C No. 10 pp. 497-504 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Electronic Circuits Keyword: adaptive voltage, transmitter, forward-body-bias (FBB), self-adjusted, threshold voltage, aggressor, jitter estimation, process-voltage-temperature (PVT), clock data recovery (CDR),
	Summary \| Full Text:PDF(5.2MB)

A 0.72pJ/bit 400μm² Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes Takuji MIKI Noriyuki MIURA Makoto NAGATA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 530-537 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: hardware security, physical random number, random masking, SAR ADC,
	Summary \| Full Text:PDF(1.5MB)

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS Takuji MIKI Noriyuki MIURA Kento MIZUTA Shiro DOSHO Makoto NAGATA
Publication: Publication Date: 2017/06/01 Vol. E100-C No. 6 pp. 560-567 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: Voltage-to-Time converter (VTC), time domain processing, CMOS, two-step transition, trip voltage,
	Summary \| Full Text:PDF(1.5MB)

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator Naoya AZUMA Shunsuke SHIMAZAKI Noriyuki MIURA Makoto NAGATA Tomomitsu KITAMURA Satoru TAKAHASHI Motoki MURAKAMI Kazuaki HORI Atsushi NAKAMURA Kenta TSUKAMOTO Mizuki IWANAMI Eiji HANKUI Sho MUROGA Yasushi ENDO Satoshi TANAKA Masahiro YAMAGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/06/01 Vol. E97-C No. 6 pp. 546-556 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: substrate coupling, power delivery network, noise interference, wireless communication,
	Summary \| Full Text:PDF(5.2MB)

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage Daisuke FUJIMOTO Noriyuki MIURA Makoto NAGATA Yuichi HAYASHI Naofumi HOMMA Takafumi AOKI Yohei HORI Toshihiro KATASHITA Kazuo SAKIYAMA Thanh-Ha LE Julien BRINGER Pirouz BAZARGAN-SABET Shivam BHASIN Jean-Luc DANGER
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 272-279 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: information leakage, side-channel attack, correlation power analysis, advance encryption standard,
	Summary \| Full Text:PDF(4MB)

6 W/25 mm² Wireless Power Transmission for Non-contact Wafer-Level Testing Andrzej RADECKI Hayun CHUNG Yoichi YOSHIDA Noriyuki MIURA Tsunaaki SHIDEI Hiroki ISHIKURO Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 668-676 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: inductive coupling, inductive power transfer, wafer-level testing,
	Summary \| Full Text:PDF(4.3MB)

Constant Magnetic Field Scaling in Inductive-Coupling Data Link Daisuke MIZOGUCHI Noriyuki MIURA Hiroki ISHIKURO Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/02/01 Vol. E91-C No. 2 pp. 200-205 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: inductive coupling, constant magnetic field, low power, high data rate, SiP,
	Summary \| Full Text:PDF(701.9KB)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link Kiichi NIITSU Noriyuki MIURA Mari INOUE Yoshihiro NAKAGAWA Masamoto TAGO Masayuki MIZUNO Takayasu SAKURAI Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 829-835 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Analog and Communications Keyword: low power, daisy chain, inductive coupling, wide bandwidth,
	Summary \| Full Text:PDF(1.7MB)

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology Daisuke MIZOGUCHI Noriyuki MIURA Takayasu SAKURAI Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 320-326 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Interface and Interconnect Techniques Keyword: inductive coupling, wireless superconnect, 3D-stacked chips, low power, high bandwidth,
	Summary \| Full Text:PDF(904KB)

TCAD Driven Drain Engineering for Hot Carrier Reduction of 3.3 V I/O PMOSFET Noriyuki MIURA Hirotaka KOMATSUBARA Marie MOCHIZUKI Hirokazu HAYASHI Koichi FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/03/01 Vol. E86-C No. 3 pp. 447-452 Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02)) Category: Keyword: hot carrier degradation, I/O transistor, drain avalanche hot carrier, channel hot hole, photo-mask reduction,
	Summary \| Full Text:PDF(1.2MB)

A New Non-Pair Diffusion Based Dopant Pile-up Model for Process Designers and Its Prediction Accuracy Hirokazu HAYASHI Noriyuki MIURA Hirotaka KOMATSUBARA Marie MOCHIZUKI Koichi FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/03/01 Vol. E86-C No. 3 pp. 453-458 Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02)) Category: Keyword: RSCE, simple model, dopant pile-up, threshold voltage,
	Summary \| Full Text:PDF(1.5MB)

A Simplified Dopant Pile-Up Model for Process Simulators Hirokazu HAYASHI Noriyuki MIURA Hirotaka KOMATSUBARA Marie MOCHIZUKI Koichi FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/12/01 Vol. E85-C No. 12 pp. 2117-2122 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: RSCE, simple model, dopant pile-up, threshold voltage,
	Summary \| Full Text:PDF(1.1MB)

A Simplified Process Modeling for Reverse Short Channel Effect of Threshold Voltage of MOSFET Hirokazu HAYASHI Noriyuki MIURA Hirotaka KOMATSUBARA Koichi FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/09/01 Vol. E84-C No. 9 pp. 1234-1239 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: RSCE, simple model, dopant pile-up, threshold voltage,
	Summary \| Full Text:PDF(756.1KB)

Systematic Yield Simulation Methodology Applied to Fully-Depleted SOI MOSFET Process Noriyuki MIURA Hirokazu HAYASHI Koichi FUKUDA Kenji NISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/08/25 Vol. E83-C No. 8 pp. 1288-1294 Type of Manuscript: Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99)) Category: Simulation Methodology and Environment Keyword: fully-depleted SOI, floating-body effect, parasitic channel leakage, systematic yield, process optimization,
	Summary \| Full Text:PDF(1.1MB)