Noriyoshi YOSHIDA


PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model--Design and Implementation of Its Prototype Processor
Kazuya TANIGAWA Tetsuo HIRONAKA Akira KOJIMA Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 830-840
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
reconfigurable architectureI-PARS execution modelgeneral purposePARS architecturedesign and implementation
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Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities
Tetsushi KOIDE Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1419-1430
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
over-the-cell routingnon-uniform over-the-cell routing capacityplanar routingH-V routingdynamic programming
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An Efficient Timing-Driven Global Routing Method for Standard Cell Layout
Tetsushi KOIDE Takeshi SUZUKI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1410-1418
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
standard cell layoutglobal routingtiming constraintsslack distribution0-1 integer linear programming
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A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
Tetsushi KOIDE Yoshinori KATSURA Katsumi YAMATANI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2053-2057
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
building block layoutfloorplanningrelative placementtopological constraintstrong respecttentative insertionblock reshaping
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A Graph Bisection Algorithm Based on Subgraph Migration
Kazunori ISOMOTO Yoshiyasu MIMASA Shin'ichi WAKABAYASHI Tetsushi KOIDE Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2039-2044
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
graph partitioningheuristic algorithmKernighan-Lin algorithmFiduccia-Mattheyses algorithmsubgraph migration
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An Optimal Channel Pin Assignment Algorithm for Hierarchical Building-Block Layout Design
Tetsushi KOIDE Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1636-1644
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
channel pin assignmentchannel routingchannel densitybuilding-block layout
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An Efficient Hypergraph Bisection Algorithm for Partitioning VLSI Circuits
Yoko KAMIDOI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1272-1279
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hypergraphbisectionnetgraphcircuit partitioning
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On Analytical Evaluation of Cluster-Based Routing for Real-Time Computer Networks
Kenji ISHIDA Jun'ichi MIYAO Tohru KIKUNO Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/07/25
Vol. E72-E  No. 7  pp. 843-851
Type of Manuscript:  PAPER
Category: Computer Networks
Keyword: 
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A Simulation Experiment on Optimality of Path Length for Hierarchical Routing Schemes
Kenji ISHIDA Jun'ichi MIYAO Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/01/25
Vol. E72-E  No. 1  pp. 4-6
Type of Manuscript:  LETTER
Category: Graphs and Networks
Keyword: 
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On the Usefulness of Additional Vias in Multilayer Printed Wiring Boards
Mohsen GHAMESHLU Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/11/25
Vol. E71-E  No. 11  pp. 1091-1094
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
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A Reduction Technique for Layers in Multilayer Printed Wiring Boards--Using Additional Vias between Grid Points--
Mohsen GHAMESHLU Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/09/25
Vol. E71-E  No. 9  pp. 887-894
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
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Single-Row Routing for Net Lists with a Specified Density Employing Backward Moves
Mohsen GHAMESHLU Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/08/25
Vol. E71-E  No. 8  pp. 747-749
Type of Manuscript:  LETTER
Category: Algorithm and Computational Complexity
Keyword: 
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An Extended Layering Algorithm for Multilayer Printed Wiring Boards
Mohsen GHAMESHLU Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/10/25
Vol. E70-E  No. 10  pp. 906-908
Type of Manuscript:  LETTER
Category: Computer Applications
Keyword: 
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A Programmable Pattern Matching Machine for High Speed Recognition of Regular Sets
Shin'ichi WAKABAYASHI Tohru KIKUNO Noriyoshi YOSHIDA Takashi FUJII 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1984/07/25
Vol. E67-E  No. 7  pp. 363-370
Type of Manuscript:  PAPER
Category: VLSI Algorithms
Keyword: 
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Paralle Merge Algorithm Suitable for VLSI Implementation
Shin'ichi WAKABAYASHI Tohru KIKUNO Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1984/04/25
Vol. E67-E  No. 4  pp. 234-235
Type of Manuscript:  LETTER
Category: VLSI Algorithms
Keyword: 
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The NP-Completeness of the Dominating Set Problem in Cubic Planer Graphs
Tohru KIKUNO Noriyoshi YOSHIDA Yoshiaki KAKUDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1980/06/25
Vol. E63-E  No. 6  pp. 443-444
Type of Manuscript:  LETTER
Category: Automata and Languages
Keyword: 
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Locking Protocol for Concurrent Access in B*-Trees
Tohru KIKUNO Noriyoshi YOSHIDA Kazumasa TANAKA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1980/01/25
Vol. E63-E  No. 1  pp. 9-15
Type of Manuscript:  PAPER
Category: Computers
Keyword: 
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Design of Fail-Safe Asynchronous Sequential Machine
Hiroshi MASUYAMA Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1977/10/25
Vol. E60-E  No. 10  pp. 527-532
Type of Manuscript:  PAPER
Category: Computers
Keyword: 
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