Norihiko KOTANI


Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation
Yasumasa TSUKAMOTO Tatsuya KUNIKIYO Koji NII Hiroshi MAKINO Shuhei IWADE Kiyoshi ISHIKAWA Yasuo INOUE Norihiko KOTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 439-446
Type of Manuscript:  Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
embedded SRAMscaling merit3-dimensional interconnect simulation50 and 70 nm technology nodes
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Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits
Ken-ichiro SONODA Motoaki TANIZAWA Kiyoshi ISHIKAWA Norihiko KOTANI Tadashi NISHIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/08/25
Vol. E83-C  No. 8  pp. 1317-1323
Type of Manuscript:  Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Circuit Applications
Keyword: 
electrostatic dischargeelectrothermal simulationcircuit simulation
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Design and Development of 3-Dimensional Process Simulator
Tetsunori WADA Norihiko KOTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 839-847
Type of Manuscript:  INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
semiconductorprocess simulatordesignfile format
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Two-Dimensional Device Simulation of 0.1 µm Thin-Film SOI MOSFET's
Hans-Oliver JOACHIM Yasuo YAMAGUCHI Kiyoshi ISHIKAWA Norihiko KOTANI Tadashi NISHIMURA Katsuhiro TSUKAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/12/25
Vol. E75-C  No. 12  pp. 1498-1505
Type of Manuscript:  Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices)
Category: Deep Sub-micron SOI CMOS
Keyword: 
thin-film SOI MOSFET'sminiaturized devicesdevice simulation
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The Impact Ionization Calculated by Monte Carlo Technique
Masayoshi SHIRAHATA Norihiko KOTANI Yoichi AKASAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/06/25
Vol. E74-C  No. 6  pp. 1656-1661
Type of Manuscript:  Special Section PAPER (Special Issue on Device and Process Simulation for Ultra Large Scale Integration)
Category: 
Keyword: 
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Oblique Rotating Ion Implantation Simulation for the Drain Formation of Gate/N- Overlapped LDD MOSFET's Using the Monte Carlo Method
Tatsuya KUNIKIYO Masato FUJINAGA Tetsuya UCHIDA Norihiko KOTANI Yoichi AKASAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/06/25
Vol. E74-C  No. 6  pp. 1662-1671
Type of Manuscript:  Special Section PAPER (Special Issue on Device and Process Simulation for Ultra Large Scale Integration)
Category: 
Keyword: 
 Summary | Full Text:PDF