IEICE Trans

Nobuyuki HIKICHI

Optimal Instruction Set Design through Adaptive Detabase Generation Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 347-353 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: ASIP, HW/SW partioning, performance estimation, adaptive database generation,
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An Instruction Set Optimization Algorithm for Pipelined ASIPs Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 pp. 1707-1714 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: ASIP, pipelined architecture, HW/SW partitioning, performance estimation, PEAS-I system,
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An Efficient Scheduling Algorithm for Pipelined Instruction Set Processor and Its Application to ASIP Hardware/Software Codesign Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI Yoshimichi HONMA Jun SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/25 Vol. E78-A No. 3 pp. 353-362 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: scheduling, pipeline hazards, HW/SW partitioning, ASIP, performance estimation, PEAS-I system,
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PEAS-I： A Hardware/Software Codesign System for ASIP Development Jun SATO Alauddin Y. ALOMARY Yoshimichi HONMA Takeharu NAKATA Akichika SHIOMI Nobuyuki HIKICHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/03/25 Vol. E77-A No. 3 pp. 483-491 Type of Manuscript: Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems) Category: Computer Aided Design (CAD) Keyword: ASIP, hardware/software codesign, PEAS-I, CPU core design automation, application program development tool generation,
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An Integer Programming Approach to Instruction Set Selection Problem Alauddin Y. ALOMARY Masaharu IMAI Jun SATO Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1849-1857 Type of Manuscript: PAPER Category: VLSI Design Technology Keyword: ASIP, VLSI CAD, instruction set optimization, branch-and-bound method,
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An ASIP Instruction Set Optimization Algorithm with Functional Module Sharing Constraint Alauddin Y. ALOMARY Masaharu IMAI Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1713-1720 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: ASIP, instruction set optimization, branch-and-bound method, functional module sharing, PEAS system,
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Proposal of a New Design Environment for Application Specific Integrated Processor: IDEAS Jun SATO Masaharu IMAI Tetsuya HAKATA Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/05/25 Vol. E74-A No. 5 pp. 1014-1016 Type of Manuscript: Special Section LETTER (Special Issue on 1991 Spring Natl. Conv. IEICE) Category: VLSI Design Keyword:
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