Nobuyuki HIKICHI


Optimal Instruction Set Design through Adaptive Detabase Generation
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 347-353
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
ASIP, HW/SW partioningperformance estimationadaptive database generation
 Summary | Full Text:PDF

An Instruction Set Optimization Algorithm for Pipelined ASIPs
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1707-1714
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ASIPpipelined architectureHW/SW partitioningperformance estimationPEAS-I system
 Summary | Full Text:PDF

An Efficient Scheduling Algorithm for Pipelined Instruction Set Processor and Its Application to ASIP Hardware/Software Codesign
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI Yoshimichi HONMA Jun SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3  pp. 353-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
schedulingpipeline hazardsHW/SW partitioningASIPperformance estimationPEAS-I system
 Summary | Full Text:PDF

PEAS-I: A Hardware/Software Codesign System for ASIP Development
Jun SATO Alauddin Y. ALOMARY Yoshimichi HONMA Takeharu NAKATA Akichika SHIOMI Nobuyuki HIKICHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 483-491
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Computer Aided Design (CAD)
Keyword: 
ASIPhardware/software codesignPEAS-ICPU core design automationapplication program development tool generation
 Summary | Full Text:PDF

An Integer Programming Approach to Instruction Set Selection Problem
Alauddin Y. ALOMARY Masaharu IMAI Jun SATO Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1849-1857
Type of Manuscript:  PAPER
Category: VLSI Design Technology
Keyword: 
ASIPVLSI CADinstruction set optimizationbranch-and-bound method
 Summary | Full Text:PDF

An ASIP Instruction Set Optimization Algorithm with Functional Module Sharing Constraint
Alauddin Y. ALOMARY Masaharu IMAI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1713-1720
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ASIPinstruction set optimizationbranch-and-bound methodfunctional module sharingPEAS system
 Summary | Full Text:PDF

Proposal of a New Design Environment for Application Specific Integrated Processor: IDEAS
Jun SATO Masaharu IMAI Tetsuya HAKATA Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/05/25
Vol. E74-A  No. 5  pp. 1014-1016
Type of Manuscript:  Special Section LETTER (Special Issue on 1991 Spring Natl. Conv. IEICE)
Category: VLSI Design
Keyword: 
 Summary | Full Text:PDF