Nobuhiko SUGINO


Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation
Takefumi MIYOSHI Nobuhiko SUGINO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1967-1976
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
dynamic reconfigurable processorcompilerautomatic context generation
 Summary | Full Text:PDF(698.6KB)

Memory Allocation and Code Optimization Methods for DSPs with Indexed Auto-Modification
Yuhei KANEKO Nobuhiko SUGINO Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 846-854
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
indirect addressingmemory addressingmemory allocationscheduling method
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Unified Phase Compiler by Use of 3-D Representation Space
Takefumi MIYOSHI Nobuhiko SUGINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 838-845
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
optimized compilerVLIWDSPalgorithm
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Code Optimization Technique for Indirect Addressing DSPs with Consideration in Local Computational Order and Memory Allocation
Nobuhiko SUGINO Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8  pp. 1960-1968
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword: 
DSP compilerindirect memory addressingmemory allocationcode optimization
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Memory Allocation Method for Indirect Addressing DSPs with 2 Update Operations
Nakaba KOGURE Nobuhiko SUGINO Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/03/25
Vol. E81-A  No. 3  pp. 420-428
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
DSP compilermemory addressingcode optimization
 Summary | Full Text:PDF(680.3KB)

DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses
Nobuhiko SUGINO Hironobu MIYAZAKI Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/12/25
Vol. E80-A  No. 12  pp. 2562-2571
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
digital signal processorcompilercode optimizationmemory addressing
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DSP Code Optimization Utilizing Memory Addressing Operation
Nobuhiko SUGINO Satoshi IIMURO Akinori NISHIHARA Nobuo FUJII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/08/25
Vol. E79-A  No. 8  pp. 1217-1224
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
DSP compilercode optimizationmemory addressing
 Summary | Full Text:PDF(637.5KB)

DSP Compiler for Matrix and Vector Expressions with Automatic Computational Ordering
Nobuhiko SUGINO Seiji OHBI Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/08/25
Vol. E78-A  No. 8  pp. 989-995
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
DSP compilercode optimizationmatrix and vector computation
 Summary | Full Text:PDF(507.8KB)

Frequency-Domain Simulator of Digital Networks from the Structural Description
Nobuhiko SUGINO Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1804-1806
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Signals, Circuits and Images
Keyword: 
 Summary | Full Text:PDF(179.2KB)

Computational Ordering of Digital Networks under Pipeline Constraints and Its Application to DSP Compilers
Nobuhiko SUGINO Seiji OHBI Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E  No. 12  pp. 1299-1306
Type of Manuscript:  Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: Digital Signal Processing
Keyword: 
 Summary | Full Text:PDF(643.1KB)