IEICE Trans

Nobuhiko SUGINO

Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation Takefumi MIYOSHI Nobuhiko SUGINO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1967-1976 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable Device and Design Tools Keyword: dynamic reconfigurable processor, compiler, automatic context generation,
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Memory Allocation and Code Optimization Methods for DSPs with Indexed Auto-Modification Yuhei KANEKO Nobuhiko SUGINO Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 846-854 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: indirect addressing, memory addressing, memory allocation, scheduling method,
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Unified Phase Compiler by Use of 3-D Representation Space Takefumi MIYOSHI Nobuhiko SUGINO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 838-845 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: optimized compiler, VLIW, DSP, algorithm,
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Code Optimization Technique for Indirect Addressing DSPs with Consideration in Local Computational Order and Memory Allocation Nobuhiko SUGINO Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/08/01 Vol. E84-A No. 8 pp. 1960-1968 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Implementations of Signal Processing Systems Keyword: DSP compiler, indirect memory addressing, memory allocation, code optimization,
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Memory Allocation Method for Indirect Addressing DSPs with 2 Update Operations Nakaba KOGURE Nobuhiko SUGINO Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 pp. 420-428 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: DSP compiler, memory addressing, code optimization,
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DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses Nobuhiko SUGINO Hironobu MIYAZAKI Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/12/25 Vol. E80-A No. 12 pp. 2562-2571 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: digital signal processor, compiler, code optimization, memory addressing,
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DSP Code Optimization Utilizing Memory Addressing Operation Nobuhiko SUGINO Satoshi IIMURO Akinori NISHIHARA Nobuo FUJII
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/08/25 Vol. E79-A No. 8 pp. 1217-1224 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: DSP compiler, code optimization, memory addressing,
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DSP Compiler for Matrix and Vector Expressions with Automatic Computational Ordering Nobuhiko SUGINO Seiji OHBI Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/08/25 Vol. E78-A No. 8 pp. 989-995 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: DSP compiler, code optimization, matrix and vector computation,
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Frequency-Domain Simulator of Digital Networks from the Structural Description Nobuhiko SUGINO Akinori NISHIHARA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/11/25 Vol. E73-E No. 11 pp. 1804-1806 Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE) Category: Signals, Circuits and Images Keyword:
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Computational Ordering of Digital Networks under Pipeline Constraints and Its Application to DSP Compilers Nobuhiko SUGINO Seiji OHBI Akinori NISHIHARA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1989/12/25 Vol. E72-E No. 12 pp. 1299-1306 Type of Manuscript: Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems) Category: Digital Signal Processing Keyword:
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