Noboru SAKIMURA


Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
Ryusuke NEBASHI Noboru SAKIMURA Tadahiko SUGIBAYASHI Naoki KASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 417-422
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
MRAMembedded memorySoCsystem LSI
 Summary | Full Text:PDF

MRAM Applications Using Unlimited Write Endurance
Tadahiko SUGIBAYASHI Takeshi HONDA Noboru SAKIMURA Shuichi TAHARA Naoki KASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1936-1940
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Next-Generation Memory for SoC
Keyword: 
MRAMdrive recorderasynchronous SRAMpseudo SRAMdemo system
 Summary | Full Text:PDF

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode
Takeshi HONDA Noboru SAKIMURA Tadahiko SUGIBAYASHI Naoki KASAI Hiromitsu HADA Shu-ichi TAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/02/01
Vol. E90-C  No. 2  pp. 531-535
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
MRAMtoggleintermittent failure
 Summary | Full Text:PDF

MRAM Writing Circuitry to Compensate for Thermal Variation of Magnetization Reversal Current
Takeshi HONDA Noboru SAKIMURA Tadahiko SUGIBAYASHI Hideaki NUMATA Sadahiko MIURA Hiromitsu HADA Shuichi TAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 612-617
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
MRAMmagnetization reversal currentthermal-variation compensation
 Summary | Full Text:PDF

Multibit Delta-Sigma Architectures with Two-Level Feedback Loop Using a Dual-Quantization Architecture
Noboru SAKIMURA Motoi YAMAGUCHI Michio YOTSUYANAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 497-505
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
Category: 
Keyword: 
A/D converterdelta-sigma modulatornoise-shapingdual-quantization architecture
 Summary | Full Text:PDF