Nguyen Ngoc BINH


A New Approach to Embedded Software Optimization Based on Reverse Engineering
Nguyen Ngoc BINH Pham Van HUONG Bui Ngoc HAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/06/01
Vol. E98-D  No. 6  pp. 1166-1175
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
embedded software optimizationreverse engineeringpower consumptionperformanceinstruction schedulinggenetic algorithm
 Summary | Full Text:PDF

Optimal Instruction Set Design through Adaptive Detabase Generation
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 347-353
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
ASIP, HW/SW partioningperformance estimationadaptive database generation
 Summary | Full Text:PDF

An Instruction Set Optimization Algorithm for Pipelined ASIPs
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1707-1714
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ASIPpipelined architectureHW/SW partitioningperformance estimationPEAS-I system
 Summary | Full Text:PDF

An Efficient Scheduling Algorithm for Pipelined Instruction Set Processor and Its Application to ASIP Hardware/Software Codesign
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI Yoshimichi HONMA Jun SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3  pp. 353-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
schedulingpipeline hazardsHW/SW partitioningASIPperformance estimationPEAS-I system
 Summary | Full Text:PDF