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An Optimization Algorithm for High Performance ASIP Design with Considering the RAM and ROM Sizes
Nguyen Ngoc BINH Masaharu IMAI Yoshinori TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2612-2620
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design
ASIPHW/SW partitioningperformance estimationRAMROM
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