Nattha SRETASEREEKUL


Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design
Nattha SRETASEREEKUL Hiroshi SAITO Euiseok KIM Metehan OZCAN Masashi IMAI Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3028-3037
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
asynchronous controllerslogic synthesisControl Data Flow Graphs (CDFGs)Signal Transition Graphs (STGs)
 Summary | Full Text:PDF

Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits
Nattha SRETASEREEKUL Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 900-907
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
isochronic forksasynchronous circuitsquasi-delay-insensitive circuits
 Summary | Full Text:PDF