IEICE Trans

Naoya WATANABE

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/10/01 Vol. E88-C No. 10 pp. 2020-2027 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: embedded memory, DRAM, voltage margin, low voltage, system on chip,
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An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 624-634 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: embedded DRAM, various DRAM macros, low voltage operation, short TAT, BIST,
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A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/09/01 Vol. E85-C No. 9 pp. 1697-1708 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: embedded DRAM, system on chip, 3-D graphics concurrent operation,
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Scalable Internet Backbone Using Multi-Gigabit ATM-Based Connectionless Switching Shigehiko USHIJIMA Hiroyuki ICHIKAWA Katsunori NORITAKE Naoya WATANABE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1998/02/25 Vol. E81-B No. 2 pp. 324-332 Type of Manuscript: Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN) Category: ATM switch interworking Keyword: connectionless, Internet, router, ATM, gigabit, IP,
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A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU Katsumi DOSAKA Akira YAMAZAKI Naoya WATANABE Hideaki ABE Jun OHTANI Toshiyuki OGAWA Kazunori ISHIHARA Masaki KUMANOYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 948-956 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme Hisashi IWAMOTO Naoya WATANABE Akira YAMAZAKI Seiji SAWADA Yasumitsu MURAI Yasuhiro KONISHI Hiroshi ITOH Masaki KUMANOYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 pp. 1328-1333 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: DRAM Keyword: synchronous DRAM, SDRAM, high speed DRAM, multiple-register,
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Optimum Packet Size for Message Communications in Heterogeneous Packet Switching Naoya WATANABE Yutaka YOSHIDA Joichi SAITO Toyofumi TAKENAKA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1981/10/25 Vol. E64-E No. 10 pp. 633-639 Type of Manuscript: PAPER Category: Switching Systems Keyword:
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