Naohito KOJIMA


Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays
Midori TAKANO Fumihiro MINAMI Naohito KOJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1405-1409
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
clock routingdelayskewembedded array
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Power and Area Minimization by Reorganizing CMOS Complex-Gates
Masayoshi TACHIBANA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 312-320
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
VLSI CADlogic synthesiscomplex-gatetransistor sizing
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Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization
Masaaki YAMADA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 441-446
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: DA/Architecture
Keyword: 
LSIlayouttransistor sizinglow powerCAD
 Summary | Full Text:PDF