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| Naohiko SHIMIZU
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Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser
Naohiko SHIMIZU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A
No. 12
pp. 3225-3229
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword:
logic synthesis, HDL conversion, SFL, verilog, | | | Summary | Full Text:PDF | |
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Pipelining Gauss Seidel Method for Analysis of Discrete Time Cellular Neural Networks
Naohiko SHIMIZU Gui-Xin CHENG Munemitsu IKEGAMI Yoshinori NAKAMURA Mamoru TANAKA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/08/25
Vol. E77-A
No. 8
pp. 1396-1403
Type of Manuscript:
PAPER
Category: Neural Networks
Keyword:
cellular neural networks, dynamics, numerical analysis, relaxation method, pipelining, image coding, image decoding, structural compression, regularization, communication system, | | | Summary | Full Text:PDF | |
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