IEICE Trans

Nagisa ISHIURA

CF3: Test Suite for Arithmetic Optimization of C Compilers Yusuke HIBINO Hirofumi IKEO Nagisa ISHIURA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1511-1512 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: C compiler test suite, arithmetic optimization,
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High-Level Synthesis of Software Function Calls Masanari NISHIMURA Nagisa ISHIURA Yoshiyuki ISHIMORI Hiroyuki KANBARA Hiroyuki TOMIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3556-3558 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, CCAP, hardware/software co-design, C-based design,
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FOREWORD Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3413-3414 Type of Manuscript: FOREWORD Category: Keyword:
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Register Constraint Analysis to Minimize Spill Code for Application Specific DSPs Tatsuo WATANABE Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/06/01 Vol. E84-A No. 6 pp. 1541-1544 Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000)) Category: Keyword: application specific DSP, spill code insertion, embedded system, scheduling, register constraint analysis,
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Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes Mizuki TAKAHASHI Nagisa ISHIURA Akihisa YAMADA Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2456-2463 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design and High-level Synthesis Keyword: behavioral partitioning, thread composition, behavioral synthesis,
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A Binding Algorithm for Retargetable Compilation to Non-orthogonal DSP Architectures Masayuki YAMAGUCHI Nagisa ISHIURA Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2630-2639 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Compiler Keyword: retargetable compiler, binding, non-orthogonal architecture, DSP, binary decision diagram,
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Embedded Memory Array Testing Using a Scannable Configuration Seiken YANO Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 pp. 1934-1944 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: scannable memory configuration, memory array testing, design-for-testability, scan design,
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Architecture Evaluation Based on the Datapath Structure and Parallel Constraint Masayuki YAMAGUCHI Akihisa YAMADA Toshihiro NAKAOKA Takashi KAMBE Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 pp. 1853-1860 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: performance evaluation, datapath, structure, parallel constraint,
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Application of Full Scan Design to Embedded Memory Arrays Seiken YANO Katsutoshi AKAGI Hiroki INOHARA Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 pp. 514-520 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: design-for-testability, DFT scan design, scannable memory array, memory array testing,
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Implicit Representation and Manipulation of Binary Decision Diagrams Hitoshi YAMAUCHI Nagisa ISHIURA Hiromitsu TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 354-362 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: binary decision diagram (BDD), representation of Boolean functions, logic design verification, logic synthesis, implicit representation of graphs,
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Datapath Scheduling for Behavioral Description with Conditional Branches Akihisa YAMADA Toshiki YAMAZAKI Nagisa ISHIURA Isao SHIRAKAWA Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 pp. 1999-2009 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, datapath scheduling, 0-1 integer programming problem, binary decision diagram, branch-and-bound method,
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Test Generation for Sequential Circits Using Partitioned Image Computation Hoyong CHOI Hironori MAEDA Takashi KOHARA Nagisa ISHIURA Isao SHIRAKAWA Akira MOTOHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1770-1774 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: test generation for sequential circuitt, product machine traversal method, mixed breadth-first/depth-first traversal, partitioned image computation,
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Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 pp. 1121-1127 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Test Keyword: test generation, combinational circuits, compact test sets, binary decision diagrams,
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Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 pp. 1085-1092 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, binary decision diagrams, combinational circuits,
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Research Topics and Results on Simulation for VLSI Isao SHIRAKAWA Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/07/25 Vol. E76-A No. 7 pp. 1070-1076 Type of Manuscript: Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I) Category: Keyword: VLSI, circuit simulation, logic simulation,
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Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits Nagisa ISHIURA Yutaka DEGUCHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1247-1254 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic circuits, timing verification, symbolic simulation, Boolean function manipulation,
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Linear Time Fault Simulation Algorithm Using a Content Addressable Memory Nagisa ISHIURA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 pp. 314-320 Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: fault simulation, content addressable memory, parallel computation,
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