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FOREWORD Nagisa ISHIURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A
No. 12
pp. 3413-3414
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FOREWORD Category: Keyword:
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Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams Nagisa ISHIURA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D
No. 9
pp. 1085-1092
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Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: logic synthesis, binary decision diagrams, combinational circuits, | | Summary | Full Text:PDF | |
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Research Topics and Results on Simulation for VLSI Isao SHIRAKAWA Nagisa ISHIURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/07/25
Vol. E76-A
No. 7
pp. 1070-1076
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Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I) Category: Keyword: VLSI, circuit simulation, logic simulation, | | Summary | Full Text:PDF | |
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Linear Time Fault Simulation Algorithm Using a Content Addressable Memory Nagisa ISHIURA Shuzo YAJIMA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A
No. 3
pp. 314-320
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INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: fault simulation, content addressable memory, parallel computation, | | Summary | Full Text:PDF | |
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