Murali JAYAPALA


Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
Ittetsu TANIGUCHI Praveen RAGHAVAN Murali JAYAPALA Francky CATTHOOR Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1161-1173
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
address generation unit (AGU)reconfigurable architectureASIP designarchitecture exploration
 Summary | Full Text:PDF

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling
Yuki KOBAYASHI Murali JAYAPALA Praveen RAGHAVAN Francky CATTHOOR Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 604-612
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
compilers for low energyVLIW processorsloop buffers
 Summary | Full Text:PDF