IEICE Trans

Munehiro MATSUURA

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Hisashi IWAMOTO Yasuhiro TERAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/02/01 Vol. E98-D No. 2 pp. 262-271 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: CAM, IP lookup, index generation unit, FPGA,
	Summary \| Full Text:PDF

A Packet Classifier Based on Prefetching EVMDD (k) Machines Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2243-2252 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: many core, packet classification, decision diagram, multi-valued logic,
	Summary \| Full Text:PDF

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1667-1675 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Application Keyword: pattern matching, virus scanning, index generation function, CAM,
	Summary \| Full Text:PDF

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 364-373 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: regular expression, NFA, DFA, MNFAU, FPGA,
	Summary \| Full Text:PDF

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Yoshifumi KAWAMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2048-2058 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: embedded system, branching program machine, multi-processing, BDD,
	Summary \| Full Text:PDF

A Quaternary Decision Diagram Machine: Optimization of Its Code Tsutomu SASAO Hiroki NAKAHARA Munehiro MATSUURA Yoshifumi KAWAMURA Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2026-2035 Type of Manuscript: INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Keyword: quarternary decision diagram, branching program machine,
	Summary \| Full Text:PDF

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades Munehiro MATSUURA Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2762-2769 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis and Verification Keyword: incompletely specified function, characteristic function, binary decision diagram, functional decomposition, LUT cascade,
	Summary \| Full Text:PDF

Design Methods of Radix Converters Using Arithmetic Decompositions Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/06/01 Vol. E90-D No. 6 pp. 905-914 Type of Manuscript: PAPER Category: Computer Components Keyword: radix converter, LUT cascades, FPGA, functional decomposition,
	Summary \| Full Text:PDF

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3471-3481 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: LUT cascade, bdd_for_cf, functional decomposition,
	Summary \| Full Text:PDF

A Design Algorithm for Sequential Circuits Using LUT Rings Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3342-3350 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: reconfigurable architecture, LUT cascade, BDD_for_CF, functional decomposition,
	Summary \| Full Text:PDF

A Realization of Multiple-Output Functions by a Look-Up Table Ring Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3141-3150 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: LUT cascade, LUT ring, multiple-output function, reconfigurable logic, programmable logic device,
	Summary \| Full Text:PDF

Area-Time Complexities of Multi-Valued Decision Diagrams Shinobu NAGAYAMA Tsutomu SASAO Yukihiro IGUCHI Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/05/01 Vol. E87-A No. 5 pp. 1020-1028 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: decision diagrams, the number of nodes, area-time complexity, randomly generated function, representation of logic functions,
	Summary \| Full Text:PDF

Bi-Partition of Shared Binary Decision Diagrams Munehiro MATSUURA Tsutomu SASAO Jon T. BUTLER Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2693-2700 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: shared binary decision diagram, SBDD, bi-partition, multiple-output function, decomposition,
	Summary \| Full Text:PDF

On Properties of Kleene TDDs Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-D No. 7 pp. 716-723 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Logic Simulation and Logic Optimization Keyword: binary decision diagram, ternary decision diagram, logic simulation, ternary logic,
	Summary \| Full Text:PDF