Mototaka KURIBAYASHI

SCR : SPICE Netlist Reduction Tool
Mototaka KURIBAYASHI Masaaki YAMADA Hideki TAKEUCHI Masami MURAKATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3  pp. 417-423
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SPICE, reduction, transistor, simulation, CAD, VLSI, 
 Summary | Full Text:PDF
A Hierarchical Global Router for Mscro-Block-Embedded Sea-of-Gates
Mototaka KURIBAYASHI Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1694-1704
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSI, CAD, router, hierarchical decomposition, 
 Summary | Full Text:PDF