IEICE Trans

Motoki AMAGASAKI

Relationship between Recognition Accuracy and Numerical Precision in Convolutional Neural Network Models Yasuhiro NAKAHARA Masato KIYAMA Motoki AMAGASAKI Masahiro IIDA
Publication: Publication Date: 2020/12/01 Vol. E103-D No. 12 pp. 2528-2529 Type of Manuscript: Special Section LETTER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Computer System Keyword: convolutional neural network, quantization,
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Three Dimensional FPGA Architecture with Fewer TSVs Motoki AMAGASAKI Masato IKEBE Qian ZHAO Masahiro IIDA Toshinori SUEYOSHI
Publication: Publication Date: 2018/02/01 Vol. E101-D No. 2 pp. 278-287 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Device and Architecture Keyword: three dimensional IC, 3D-FPGA, power estimation, face-down/face-up stacking,
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Enabling FPGA-as-a-Service in the Cloud with hCODE Platform Qian ZHAO Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: Publication Date: 2018/02/01 Vol. E101-D No. 2 pp. 335-343 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology and Platform Keyword: FPGA-as-a-service, hardware acceleration, open-source hardware,
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Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core Motoki AMAGASAKI Yuki NISHITANI Kazuki INOUE Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: Publication Date: 2017/04/01 Vol. E100-D No. 4 pp. 633-644 Type of Manuscript: INVITED PAPER (Special Section on Award-winning Papers) Category: Keyword: fault tolerant, fault recovery, FPGA-IP,
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SLM: A Scalable Logic Module Architecture with Less Configuration Memory Motoki AMAGASAKI Ryo ARAKI Masahiro IIDA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2500-2506 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, scalable logic module, technology mapping,
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Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC Motoki AMAGASAKI Qian ZHAO Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/02/01 Vol. E98-D No. 2 pp. 252-261 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: fault tolerant, FPGA, IP-core,
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FPGA Design Framework Combined with Commercial VLSI CAD Qian ZHAO Kazuki INOUE Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1602-1612 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: FPGA, CAD, routing,
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Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration Yoshihiro ICHINOMIYA Tsuyoshi KIMURA Motoki AMAGASAKI Morihiro KUGA Masahiro IIDA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2347-2356 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: FPGA, partial reconfiguration, fault-injection analysis, soft-error, dependability,
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COGRE: A Novel Compact Logic Cell Architecture for Area Minimization Masahiro IIDA Motoki AMAGASAKI Yasuhiro OKAMOTO Qian ZHAO Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 294-302 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: reconfigurable logic, COGRE, NPN-equivalent classes,
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An Easily Testable Routing Architecture and Prototype Chip Kazuki INOUE Masahiro KOGA Motoki AMAGASAKI Masahiro IIDA Yoshinobu ICHIDA Mitsuro SAJI Jun IIDA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 303-313 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: design for testability, homogeneous architecture, test method, prototype chip,
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A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells Masahiro IIDA Masahiro KOGA Kazuki INOUE Motoki AMAGASAKI Yoshinobu ICHIDA Mitsuro SAJI Jun IIDA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 548-556 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: reconfigurable logic, FeRAM, power-gating, non-volatile flip-flop, NV-FF, VGLC,
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