Mitsuo NAKAMURA


An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines
Nobutaro SHIBATA Mitsuo NAKAMURA 
Publication:   
Publication Date: 2018/08/01
Vol. E101-A  No. 8  pp. 1185-1196
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ATEdelay-locked loopdigital-to-time converterlinearity erroron the flyplain CMOS logictiming jittertiming vernier
 Summary | Full Text:PDF

A 280-MHz CMOS Intra-Symbol Intermittent RF Front End for Adaptive Power Reduction of Wireless Receivers According to Received-Signal Intensity in Sensor Networks
Mitsuo NAKAMURA Mamoru UGAJIN Mitsuru HARADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/01/01
Vol. E96-C  No. 1  pp. 93-101
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
intra-symbol intermittentRF front endlow powerwireless receiverRF CMOSsensor network
 Summary | Full Text:PDF

A Low-Voltage SOI-CMOS LC-Tank VCO with Double-Tuning Technique Using Lateral P-N Junction Variable Capacitance
Mitsuo NAKAMURA Hideki SHIMA Toshimasa MATSUOKA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/07/01
Vol. E85-C  No. 7  pp. 1428-1435
Type of Manuscript:  Special Section PAPER (Special Issue on Silicon RF Device & Integrated Circuit Technologies)
Category: 
Keyword: 
voltage controlled oscillatorwireless communicationCMOSSOIdouble-tuning
 Summary | Full Text:PDF