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High-Level Synthesis Using Given Datapath Information Toshiaki MIYAZAKI Mitsuo IKEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A
No. 10
pp. 1617-1625
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: control circuit, scheduling, resource allocation, RTL, CFG, DFG, | | Summary | Full Text:PDF | |
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