Minoru TOGASHI


A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
Yusuke OHTOMO Masafumi NOGAWA Kazuyoshi NISHIMURA Shunji KIMURA Tomoaki YOSHIDA Tomoaki KAWAMURA Minoru TOGASHI Kiyomi KUMOZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6  pp. 903-910
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
PONburstCDRICCID
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A 15-Gbit/s Si-Bipolar Gate Array
Ryuusuke KAWANO Minoru TOGASHI Chikara YAMAGUCHI Yoshiji KOBAYASHI Masao SUZUKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9  pp. 1203-1209
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed Electron Devices)
Category: 
Keyword: 
decision circuit4 : 1 multiplexertemperature-compensated output bufferSST-1C
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Asynchronous Transfer Mode Switching LSI Chips with 10-Gb/s Serial I/O Ports
Shigeki HINO Minoru TOGASHI Kimiyoshi YAMASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 596-600
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
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10Gbit/s, 35mV Decision IC Using 0.2µm GaAs MESFETs
Masanobu OHHATA Minoru TOGASHI Koichi MURATA Satoshi YAMAGUCHI Masao SUZUKI Kazuo HAGIMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1993/07/25
Vol. E76-B  No. 7  pp. 745-747
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1992 IEICE Fall Conference and the 1993 IEICE Spring Conference)
Category: 
Keyword: 
decision ICdecision circuitGaAs MESFETLSCFLSCFL interfaceSAINT
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