IEICE Trans

Minoru SAEKI

Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack Takeshi SUGAWARA Daisuke SUZUKI Minoru SAEKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1323-1333 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: RSA, side-channel attack, collision attack, Montgomery multiplication,
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How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers Daisuke SUZUKI Minoru SAEKI Koichi SHIMIZU Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 200-210 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: hardware architecture, differential power analysis, correlation power analysis, template attack,
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A Design Methodology for a DPA-Resistant Circuit with RSL Techniques Daisuke SUZUKI Minoru SAEKI Koichi SHIMIZU Akashi SATOH Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2497-2508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: side-channel attacks, differential power analysis, hardware countermeasure, random switching logic, CMOS logic circuit,
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Security Evaluations of MRSL and DRSL Considering Signal Delays Minoru SAEKI Daisuke SUZUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 176-183 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: DPA, data masking, dual-rail circuit, countermeasure, hardware, RSL, MRSL, DRSL,
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An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style Daisuke SUZUKI Minoru SAEKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 184-192 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: side-channel attacks, differential power analysis, hardware countermeasure, dual-rail pre-charge logic style, CMOS logic circuit,
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Leakage Analysis of DPA Countermeasures at the Logic Level Minoru SAEKI Daisuke SUZUKI Tetsuya ICHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 pp. 169-178 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: side-channel attacks, differential power analysis, hardware countermeasure, CMOS logic circuit, second-order DPA,
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Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level Daisuke SUZUKI Minoru SAEKI Tetsuya ICHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 pp. 160-168 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Side Channel Attacks Keyword: side-channel attacks, differential power analysis, hardware countermeasure, second-order DPA random switching logic, CMOS logic circuit,
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