Author List
Japanese Page
SITE TOP
Login
To browse Full-Text PDF.
>
Forgotten your password?
Menu
Search
Full-Text Search
Search(JPN)
Latest Issue
A Fundamentals
Trans.Fundamentals.
JPN Edition(in Japanese)
B Communications
Trans.Commun.
JPN Edition(in Japanese)
C Electronics
Trans.Electron.
JPN Edition(in Japanese)
D Information & Systems
Trans.Inf.&Syst.
JPN Edition(in Japanese)
Abstracts of JPN Edition
Trans.Fundamentals.
Trans.Commun.
Trans.Electron.
Trans.Inf.&Syst.
-
Archive
Volume List
Trans.Fundamentals.
Trans.Commun.
Trans.Electron.
Trans.Inf.&Syst.
Transactions (1976-1990)
Volume List [JPN Edition]
A JPN Edition(in Japanese)
B JPN Edition(in Japanese)
C JPN Edition(in Japanese)
D JPN Edition(in Japanese)
-
Editorial Board
Editorial Board
Trans.Fundamentals.
Trans.Commun.
Trans.Electron.
Trans.Inf.&Syst.
Archive
Editorial Board[JPN Edition]
A JPN Edition(in Japanese)
B JPN Edition(in Japanese)
C JPN Edition(in Japanese)
D JPN Edition(in Japanese)
Archive
-
Open Access Papers
Trans. Commun. (Free)
Trans. Commun.
Trans. Commun.(JPN Edition)
Trans. Electron. (Free)
Trans. Electron.
Trans. Electron.(JPN Edition)
Trans. Inf.&Syst. (Free)
Trans. Inf.&Syst.
Trans. Inf.&Syst.(JPN Edition)
-
Link
Subscription
For Authors
Statistics:
Accepting ratio,review period etc.
IEICE Home Page
-
Others
Citation Index
Privacy Policy
Copyright & Permissions
Copyright (c) by IEICE
Ming-Dou KER
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation
Ting-Chou LU
Ming-Dou KER
Hsiao-Wen ZAN
Publication:
Publication Date:
2017/08/01
Vol.
E100-C
No.
8
pp.
675-683
Type of Manuscript:
PAPER
Category:
Electronic Circuits
Keyword:
ultra-low voltage (ULV)
,
subthreshold region
,
voltage-controlled oscillator
,
temperature and process variation
,
Summary
|
Full Text:PDF
(4MB)
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration
Ting-Chou LU
Ming-Dou KER
Hsiao-Wen ZAN
Jen-Chieh LIU
Yu LEE
Publication:
Publication Date:
2017/01/01
Vol.
E100-A
No.
1
pp.
275-282
Type of Manuscript:
PAPER
Category:
VLSI Design Technology and CAD
Keyword:
crystal-less clock generator
,
multi-phase output
,
digital power application
,
process
,
voltage and temperature (PVT) calibration
,
Summary
|
Full Text:PDF
(2.8MB)
Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
Ming-Dou KER
Yuan-Wen HSIAO
Publication:
IEICE TRANSACTIONS on Electronics
Publication Date:
2009/03/01
Vol.
E92-C
No.
3
pp.
341-351
Type of Manuscript:
PAPER
Category:
Electronic Components
Keyword:
electrostatic discharge (ESD)
,
impedance-isolation technique
,
LC-tank
,
noise figure power gain
,
Summary
|
Full Text:PDF
(1.7MB)
Low-Capacitance and Fast Turn-on SCR for RF ESD Protection
Chun-Yu LIN
Ming-Dou KER
Guo-Xuan MENG
Publication:
IEICE TRANSACTIONS on Electronics
Publication Date:
2008/08/01
Vol.
E91-C
No.
8
pp.
1321-1330
Type of Manuscript:
Special Section PAPER (Special Section on Microelectronic Test Structures (ICMTS2007))
Category:
Keyword:
electrostatic discharge (ESD)
,
low capacitance (low-C)
,
power amplifier (PA)
,
radio-frequency (RF)
,
silicon-controlled rectifier (SCR)
,
waffle layout
,
Summary
|
Full Text:PDF
(2.1MB)
Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process
Jung-Sheng CHEN
Ming-Dou KER
Publication:
IEICE TRANSACTIONS on Electronics
Publication Date:
2008/03/01
Vol.
E91-C
No.
3
pp.
378-384
Type of Manuscript:
PAPER
Category:
Electronic Circuits
Keyword:
gate-oxide reliability
,
sample-and-hold amplifier
,
dielectric breakdown
,
bootstrapped switch
,
switched-capacitor circuit
,
Summary
|
Full Text:PDF
(1.1MB)
A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device
Ming-Dou KER
Jung-Sheng CHEN
Ching-Yun CHU
Publication:
IEICE TRANSACTIONS on Electronics
Publication Date:
2005/11/01
Vol.
E88-C
No.
11
pp.
2150-2155
Type of Manuscript:
PAPER
Category:
Electronic Circuits
Keyword:
voltage reference
,
bandgap voltage reference
,
temperature coefficient
,
PSRR (power supply rejection ratio)
,
startup circuit
,
Summary
|
Full Text:PDF
(920.2KB)
MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process
Ming-Dou KER
Kun-Hsien LIN
Che-Hao CHUANG
Publication:
IEICE TRANSACTIONS on Electronics
Publication Date:
2005/03/01
Vol.
E88-C
No.
3
pp.
429-436
Type of Manuscript:
PAPER
Category:
Semiconductor Materials and Devices
Keyword:
electrostatic discharge (ESD)
,
diode
,
poly-bounded diode
,
MOS-bounded diode
,
ESD protection
,
Summary
|
Full Text:PDF
(1.3MB)