Michitaka KAMEYAMA


Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators
Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2658-2669
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
heterogeneous multicoreFPGAcustom acceleratorsreconfigurable architecture
 Summary | Full Text:PDF(2.3MB)

Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/10/01
Vol. E97-C  No. 10  pp. 1028-1035
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
voltage-mode/current-mode hybrid designarbitrary two-variable function circuitfine-grain reconfigurable VLSI
 Summary | Full Text:PDF(1.6MB)

Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2278-2285
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
multiple-valued reconfigurable VLSIfine-grain reconfigurable VLSIglobal tree local X-net networklogic-in-memory architecture
 Summary | Full Text:PDF(1.9MB)

Synthesis of Quantum Arrays from Kronecker Functional Lattice Diagrams
Martin LUKAC Dipal SHAH Marek PERKOWSKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2262-2269
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Reversible/Quantum Computing
Keyword: 
reversible circuits synthesiskronecker latticesquantum computing
 Summary | Full Text:PDF(1MB)

Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators
Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2576-2586
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multicore processorFPGAMultimedia processingHigh-performance-computing
 Summary | Full Text:PDF(2.4MB)

A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/08/01
Vol. E96-C  No. 8  pp. 1083-1093
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
fine-grain reconfigurable VLSI architecturemultiple-valued switch blockbinary-controlled current-steering techniquecurrent-source sharing techniquecurrent-mode logic (CML)
 Summary | Full Text:PDF(4MB)

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1632-1644
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
FPGAreconfigurable LSIself-timed circuitasynchronous circuit
 Summary | Full Text:PDF(3.8MB)

A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/07/01
Vol. E96-D  No. 7  pp. 1449-1456
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
multiple-valued data transfer schemeX-netmultiple-valued current-mode logicMOS current-mode logicfine-grain reconfigurable VLSI
 Summary | Full Text:PDF(1.4MB)

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12  pp. 1872-1882
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
block matchingheterogeneous multi-coredynamically reconfigurable processordata transferaccelerator
 Summary | Full Text:PDF(4.4MB)

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates
Zhengfan XIA Shota ISHIHARA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/08/01
Vol. E95-C  No. 8  pp. 1434-1443
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
asynchronous pipelinedual-railcritical datapath
 Summary | Full Text:PDF(2.1MB)

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors
Hasitha Muthumala WAIDYASOORIYA Yosuke OHBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 354-363
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
memory allocationpartitioningreconfigurable processors
 Summary | Full Text:PDF(844.7KB)

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/10/01
Vol. E94-C  No. 10  pp. 1669-1679
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
mixed synchronous/asynchronous designreconfigurable VLSIfour-phase dual-rail encodingself-timed architectureGALS (Globally Asynchronous Locally Synchronous)
 Summary | Full Text:PDF(3.4MB)

Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions
Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1  pp. 342-351
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
memory allocationparallel data accessaddressing
 Summary | Full Text:PDF(2MB)

Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation
Hasitha Muthumala WAIDYASOORIYA Daisuke OKUMURA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2570-2580
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multi-core processortask-allocationsystem-on-chip
 Summary | Full Text:PDF(1.3MB)

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits
Nobuaki OKADA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2126-2133
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Application of Multiple-Valued VLSI
Keyword: 
multiple-valued current-mode logicfine-grain reconfigurable VLSIdirect allocationcontrol circuitsequential logic circuit
 Summary | Full Text:PDF(789.9KB)

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
Shota ISHIHARA Noriaki IDOBATA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2134-2144
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Application of Multiple-Valued VLSI
Keyword: 
dynamically programmable gate arraymulti-context switchlogic-in-memory circuitmultiple-valued threshold logicnonvolatile storagenon-destructive operation
 Summary | Full Text:PDF(2.1MB)

FOREWORD
Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2025-2025
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(53.2KB)

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Shota ISHIHARA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8  pp. 1338-1348
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
reconfigurable VLSIfield-programmable VLSILEDR (Level-Encoded Dual-Rail) encoding4-phase dual-rail encodingself-timed architecture
 Summary | Full Text:PDF(1.6MB)

Group Testing Based Detection of Web Service DDoS Attackers
Dalia NASHAT Xiaohong JIANG Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/05/01
Vol. E93-B  No. 5  pp. 1113-1121
Type of Manuscript:  Special Section PAPER (Special Section on Technology and Architecture for Sustainable Growth of the Internet)
Category: 
Keyword: 
distributed denial of servicegroup-testingintrusion detectionchange point detection
 Summary | Full Text:PDF(4.4MB)

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 539-549
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
DPGAmulti-contextasynchronous FPGA
 Summary | Full Text:PDF(1.8MB)

Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3596-3606
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesislow powerinterconnection networkgenetic algorithm
 Summary | Full Text:PDF(1.2MB)

Memory Allocation for Multi-Resolution Image Processing
Yasuhiro KOBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2386-2397
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
high-level synthesisinterconnection-aware architecturestereo vision
 Summary | Full Text:PDF(645KB)

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1419-1426
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
FPGAsreconfigurable VLSIsasynchronous architectureLEDR (Level-Encoded Dual-Rail) encoding
 Summary | Full Text:PDF(668.6KB)

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
Nobuaki OKADA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1437-1443
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
fine-grain reconfigurable VLSImultiple-valued source-coupled logicuniversal literaldirect allocation of CDFGlogic block
 Summary | Full Text:PDF(880.5KB)

Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
Masanori HARIYAMA Naoto YOKOYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 479-486
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
stereo visionschedulingallocation
 Summary | Full Text:PDF(1021.6KB)

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment
Hasitha Muthumala WAIDYASOORIYA Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 517-525
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
dynamically-programmable gate arraymulti-context FPGAconfiguration data redundancy
 Summary | Full Text:PDF(1.5MB)

FOREWORD
Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1849-1849
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(59.5KB)

A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates
Masanori HARIYAMA Sho OGATA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1655-1661
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
time-multiplexed FPGAdynamically reconfigurable architectureDPGAbit-serial architecture
 Summary | Full Text:PDF(866.4KB)

Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification
Masanori HARIYAMA Shigeo YAMADERA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1551-1558
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
automatic synthesisschedulingmodule selectiondata-path designoptimization
 Summary | Full Text:PDF(1.2MB)

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages
Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3298-3305
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
reconfigurable processorFPGAmultiple-supply-voltage scheme
 Summary | Full Text:PDF(923.3KB)

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture
Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3516-3522
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
stereo visionFPGAschedulingallocation
 Summary | Full Text:PDF(812.1KB)

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access
Masanori HARIYAMA Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1486-1491
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
stereo visionSAD (sum of absolute differences)memory allocationlogic-in-memory architecture
 Summary | Full Text:PDF(1.1MB)

Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic
Md.Munirul HAQUE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1869-1875
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable processormultiple-valued logicbit-serial architecturecurrent mode logic
 Summary | Full Text:PDF(613.6KB)

Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture
Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1897-1902
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable architectureFPGAbit-serial architecture
 Summary | Full Text:PDF(530.8KB)

Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/10/01
Vol. E85-C  No. 10  pp. 1814-1823
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
interconnection problempass-transistor networkfunctional pass gatemultiple-valued logiccontent-addressable memory
 Summary | Full Text:PDF(1.5MB)

Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 288-296
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
pass-transistor networkfunctional pass gateprecharge-evaluate logicmultipliersigned-digit adder
 Summary | Full Text:PDF(1.6MB)

Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme
Masanori HARIYAMA Seunghwan LEE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3  pp. 382-389
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion stereomemory allocationfunctional-unit allocation
 Summary | Full Text:PDF(2.5MB)

An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access
Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/12/25
Vol. E83-D  No. 12  pp. 2122-2130
Type of Manuscript:  PAPER
Category: Image Processing, Image Pattern Recognition
Keyword: 
motion stereoFPGA-based processormemory allocationfunctional unit allocation
 Summary | Full Text:PDF(1.9MB)

Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory
Masanori HARIYAMA Kazuhiro SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1722-1729
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Processors
Keyword: 
hierarchical collision detectionarea-time product minimizationCAMpath planning
 Summary | Full Text:PDF(1.4MB)

Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic
Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1662-1668
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Non-Binary Architectures
Keyword: 
pass-transistor networkfloating-gate MOS transistorlogic-in-memory structureManhattan distanceflash EEPROM technologyfour-valued full adder
 Summary | Full Text:PDF(1.6MB)

A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/11/25
Vol. E80-C  No. 11  pp. 1491-1498
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
3-D instrumentationepipolar constraintblock matching algorithmspecial-purpose VLSI processormemory interleaving
 Summary | Full Text:PDF(644.6KB)

Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control
Takahiro HANYU Satoshi KAZAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 941-947
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
54-bit multipliersigned-digit arithmeticdifferential logic circuitthreshold detectorsource-coupled pairmulti-phase clocking
 Summary | Full Text:PDF(599.6KB)

Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing
Takahiro HANYU Manabu ARAKAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 948-955
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
logic value conversion (LVC)floating-gate MOS transistorthreshold operationsingle-transistor cellfully parallel template matching
 Summary | Full Text:PDF(570.7KB)

Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate
Xiaowei DENG Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/08/25
Vol. E78-D  No. 8  pp. 951-958
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logicsuper pass gatelogic designquantum devicessuper pass transistor model
 Summary | Full Text:PDF(697KB)

FOREWORD
Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1021-1022
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(107.7KB)

High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems
Yasuaki SAWANO Bumchul KIM Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1101-1107
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
intelligent integrated systemshigh-level synthesisparallel processingminimum latencyscheduling
 Summary | Full Text:PDF(568.6KB)

A VLSI-Oriented Model-Based Robot Vision Processor for 3-D Instrumentation and Object Recognition
Yoshifumi SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1116-1122
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
special-purpose VLSIvisual feedbackimage matchingperspective projectionhighly parallel processing
 Summary | Full Text:PDF(610.5KB)

Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs
Yoshichika FUJIOKA Michitaka KAMEYAMA Nobuhiro TOMABECHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1123-1130
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
delay timemulti-operand multiply-additionreconfigurationdigital controlFPGA
 Summary | Full Text:PDF(673.7KB)

A Collision Detection Processor for Intelligent Vehicles
Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12  pp. 1804-1811
Type of Manuscript:  Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
special-purpose VLSIcontent-addressable memoryrectangular solid representation
 Summary | Full Text:PDF(650.5KB)

Design of Highly Parallel Linear Digital System for ULSI Processors
Masami NAKAJIMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1119-1125
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
locally computable combinational circuitslinear digital circuitscode assignmentunary operations
 Summary | Full Text:PDF(452.5KB)

Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel k-Ary Operation Circuits
Saneaki TAMAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1112-1118
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
multiple-valued codinglocally computable combinational circuitsk-ary operationspartition theoryredundant coding
 Summary | Full Text:PDF(521.9KB)

Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model
Takahiro HANYU Yoshikazu YABE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1126-1132
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
resonant-tunneling diode modeluniversal literalload line methodmultiple-valued PLAwired logiccurrent-mode linear summation
 Summary | Full Text:PDF(520.6KB)

Unified Scheduling of High Performance Parallel VLSI Processors for Robotics
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 904-910
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Parallel Processor Scheduling
Keyword: 
minimum-latency architecturespecial-purpose VLSI processorparallel processingcommunication timebus interconnection network
 Summary | Full Text:PDF(514.9KB)

A Minimum-Latency Linear Array FFT Processor for Robotics
Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/06/25
Vol. E76-D  No. 6  pp. 680-688
Type of Manuscript:  PAPER
Category: Speech Processing
Keyword: 
FFTcorrelationroboticsminimum latencylinear array processor
 Summary | Full Text:PDF(629.9KB)

Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory
Saneaki TAMAKI Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5  pp. 548-554
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Logic Design
Keyword: 
multiple-valued codinglocally computable circuitunary operationpartition theoryclosed chain set
 Summary | Full Text:PDF(500.8KB)

Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements
Katsuhiko SHIMABUKURO Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 463-471
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
fine-grain parallel processingsigned-digit arithmetic systemmultiple-valued circuit technologybidirectional current-mode circuits
 Summary | Full Text:PDF(624.8KB)

Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation
Makoto HONDA Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 455-462
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued MOS current-mode circuitresidue number systemlatencyparallel processingrobot vision
 Summary | Full Text:PDF(737.7KB)

Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation
Takeshi KASUGA Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 428-435
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
robust-fault-tolerant arithmetic circuitbitonic sorter three-valued distributed codingsafetyscaler multiple-valued current-mode circuit
 Summary | Full Text:PDF(758.4KB)

Prospects of Multiple-Valued VLSI Processors
Takahiro HANYU Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 383-392
Type of Manuscript:  INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
submicron VLSIinterconnection delaymultiple-valued hardware algorithmparallel VLSI processorMVL arithmetic and logic circuits
 Summary | Full Text:PDF(981KB)

Design of a Multiple-Valued VLSI Processor for Digital Control
Katsuhiko SHIMABUKURO Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/09/25
Vol. E75-D  No. 5  pp. 709-717
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
parallel-structure-based VLSI processorsigned-digit arithmetic systemmultiple-valued circuit technologybidirectional current-mode circuits
 Summary | Full Text:PDF(640.3KB)

Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/06/25
Vol. E75-A  No. 6  pp. 712-719
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
Category: Robot Electronics
Keyword: 
minimum-delay-time architectureVLSI processor for roboticsparallel processingparallel communicationmultiple bus interconnection networks
 Summary | Full Text:PDF(555.1KB)

Highly Parallel Collision Detection Processor for Intelligent Robots
Michitaka KAMEYAMA Tadao AMADA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 398-404
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF(572.7KB)

Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation
Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3819-3828
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Dedicated Processors
Keyword: 
 Summary | Full Text:PDF(822.5KB)

A Special-Purpose LSI for Inverse Kinematics Computation
Michitaka KAMEYAMA Takao MATSUMOTO Hideki EGAMI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3829-3837
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Dedicated Processors
Keyword: 
 Summary | Full Text:PDF(853.6KB)

A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier
Michitaka KAMEYAMA Oluwole ADEGBENRO Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1985/01/25
Vol. E68-E  No. 1  pp. 14-21
Type of Manuscript:  PAPER
Category: Signal Processing
Keyword: 
 Summary | Full Text:PDF(538.7KB)