Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/01/01 Vol. E96-CNo. 1pp. 108-114 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: random access memory, system-on-chip, redundancy, fuse,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-ANo. 12pp. 2463-2471 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: memory BIST, BISR, embedded SRAM, area per good die, iterative improvement algorithm,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-ANo. 12pp. 3318-3323 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: BIST, test pattern generator, neighborhood pattern, LFSR, reseeding,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-DNo. 10pp. 1506-1514 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: delay testing, path selection, fault simulation, test generation, path-status graph,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-DNo. 7pp. 668-674 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Built-in Self-Test Keyword: test points, BIST, optimization, testability,
