IEICE Trans

Michihiro YAMADA

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM Fukashi MORISHITA Yasuo YAMAGUCHI Takahisa EIMORI Toshiyuki OASHI Kazutami ARIMOTO Yasuo INOUE Tadashi NISHIMURA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/25 Vol. E82-C No. 3 pp. 544-552 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Silicon Devices Keyword: SOI-DRAM, floating body, high speed, low power, data retention characteristics,
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Interface Technologies for Memories and ASICs -- Review and Future Direction -- Yasuhiro KONISHI Yasunobu NAKASE Katsushi ASAHINA Makoto TANIGUCHI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/25 Vol. E82-C No. 3 pp. 438-447 Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Keyword: IO interface, LVTTL, SSTL, SLDRAM, D-RDRAM, PCI, AGP, GTL, HSTL, LVDS,
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Large Scale Embedded DRAM Technology Akira YAMAZAKI Tadato YAMAGATA Yutaka ARITA Makoto TANIGUCHI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 pp. 750-758 Type of Manuscript: INVITED PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: DRAM Keyword: embedded DRAM, system on chip, system LSI,
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A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs Kiyohiro FURUTANI Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Hideyuki OZAKI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 pp. 582-589 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: DRAM, test, redundancy,
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A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology Kunihiko KOZARU Atsushi KINOSHITA Tomohisa WADA Yutaka ARITA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 pp. 566-572 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: super-CMOS, high-speed SRAM, reference voltage generator, voltage down converter,
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A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 743-749 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: integrated electronics, high density SRAM, hierarchical bit line organization, T-shaged bit line,
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111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 735-742 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: memory, synchronous SRAM, high speed SRAM, low power, clock,
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A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories Tadato YAMAGATA Masaaki MIHARA Takeshi HAMAMOTO Yasumitsu MURAI Toshifumi KOBAYASHI Michihiro YAMADA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 pp. 1657-1664 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content addressable memory, associative memory, dynamic memory, redundancy,
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An Intelligent Cache Memory Chip Suitable for Logical Inference Kenichi YASUDA Kiyohiro FURUTANI Atsushi MAEDA Shoichi WAKANO Hiroshi NAKASHIMA Yasutaka TAKEDA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/11/25 Vol. E74-C No. 11 pp. 3796-3802 Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: System VLSI Keyword:
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