IEICE Trans

Michihiro KOIBUCHI

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System Kohei ITO Kensuke IIZUKA Kazuei HIRONAKA Yao HU Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2021/12/01 Vol. E104-D No. 12 pp. 2029-2039 Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Keyword: multi-FPGA, multi-FPGA communication, circuit-switched network, STDM switch,
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An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs Tomoya ITSUBO Michihiro KOIBUCHI Hideharu AMANO Hiroki MATSUTANI
Publication: Publication Date: 2021/12/01 Vol. E104-D No. 12 pp. 2057-2067 Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Keyword: deep learning, FPGA switch, remote GPU,
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Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks Ryuta KAWANO Ryota YASUDO Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2020/12/01 Vol. E103-D No. 12 pp. 2471-2479 Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Computer System Keyword: interconnection networks, warehouse-scale computing, data centers,
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Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies Yao HU Michihiro KOIBUCHI
Publication: Publication Date: 2020/12/01 Vol. E103-D No. 12 pp. 2480-2493 Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Computer System Keyword: high-performance computing (HPC), interconnection network, topology embedding, job scheduling,
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Efficient Two-Opt Collective-Communication Operations on Low-Latency Random Network Topologies Ke CUI Michihiro KOIBUCHI
Publication: Publication Date: 2020/12/01 Vol. E103-D No. 12 pp. 2435-2443 Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking) Category: Fundamentals of Information Systems Keyword: multicast, random network topology, interconnection network, two-opt algorithm,
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A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks Ryuta KAWANO Ryota YASUDO Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2020/01/01 Vol. E103-D No. 1 pp. 101-110 Type of Manuscript: PAPER Category: Computer System Keyword: interconnection networks, deadlock-free routing algorithm, high performance computing, irregular networks, virtual channels,
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FOREWORD Michihiro KOIBUCHI
Publication: Publication Date: 2019/12/01 Vol. E102-D No. 12 pp. 2280-2280 Type of Manuscript: FOREWORD Category: Keyword:
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Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems Yao HU Michihiro KOIBUCHI
Publication: Publication Date: 2019/02/01 Vol. E102-D No. 2 pp. 247-260 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: parallel computing, interconnection network, circuit switching, time division multiplexing (TDM), end-to-end latency,
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Enhancing Job Scheduling on Inter-Rackscale Datacenters with Free-Space Optical Links Yao HU Michihiro KOIBUCHI
Publication: Publication Date: 2018/12/01 Vol. E101-D No. 12 pp. 2922-2932 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Information networks Keyword: rackscale architecture, datacenter network, free-space optics, job scheduling,
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Proxy Responses by FPGA-Based Switch for MapReduce Stragglers Koya MITSUZUKA Michihiro KOIBUCHI Hideharu AMANO Hiroki MATSUTANI
Publication: Publication Date: 2018/09/01 Vol. E101-D No. 9 pp. 2258-2268 Type of Manuscript: PAPER Category: Computer System Keyword: FPGA, MapReduce, straggler,
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A Layout-Oriented Routing Method for Low-Latency HPC Networks Ryuta KAWANO Hiroshi NAKAHARA Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2017/12/01 Vol. E100-D No. 12 pp. 2796-2807 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Interconnection networks Keyword: high performance computing, network topology, interconnection networks,
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A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing Ryuta KAWANO Hiroshi NAKAHARA Seiichi TADE Ikki FUJIWARA Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1798-1806 Type of Manuscript: PAPER Category: Computer System Keyword: deadlock-free routing, high performance computing, time complexity,
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Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface Hiroshi NAKAHARA Tomoya OZAKI Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/12/01 Vol. E99-D No. 12 pp. 2871-2880 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Architecture Keyword: inductive coupling interconnect, interconnection network, network on chip,
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Job Mapping and Scheduling on Free-Space Optical Networks Yao HU Ikki FUJIWARA Michihiro KOIBUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/11/01 Vol. E99-D No. 11 pp. 2694-2704 Type of Manuscript: PAPER Category: Computer System Keyword: job mapping, interconnection networks, free-space optics, high-performance computing,
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Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems Akram BEN AHMED Hiroki MATSUTANI Michihiro KOIBUCHI Kimiyoshi USAMI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 pp. 909-917 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: Network-on-Chips, multi-Vdd, low power networks,
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Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks Thao-Nguyen TRUONG Khanh-Van NGUYEN Ikki FUJIWARA Michihiro KOIBUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/05/01 Vol. E99-D No. 5 pp. 1275-1284 Type of Manuscript: PAPER Category: Computer System Keyword: Network expandability, network topologies, small-world networks, interconnection networks, high-performance computing,
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New Directions for a Japanese Academic Backbone Network Shigeo URUSHIDANI Shunji ABE Kenjiro YAMANAKA Kento AIDA Shigetoshi YOKOYAMA Hiroshi YAMADA Motonori NAKAMURA Kensuke FUKUDA Michihiro KOIBUCHI Shigeki YAMADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/03/01 Vol. E98-D No. 3 pp. 546-556 Type of Manuscript: INVITED PAPER (Special Section on the Architectures, Protocols, and Applications for the Future Internet) Category: Keyword: 100-Gigabit Ethernet, MPLS-TP, SDN, multi-layer network, security, cloud service, performance accelerator, network monitoring,
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The Case for Network Coding for Collective Communication on HPC Interconnection Networks Ahmed SHALABY Ikki FUJIWARA Michihiro KOIBUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/03/01 Vol. E98-D No. 3 pp. 661-670 Type of Manuscript: PAPER Category: Information Network Keyword: interconnection networks, collective communication, network coding, high-performance computing,
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A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation Ahmadou Dit Adi CISSE Michihiro KOIBUCHI Masato YOSHIMI Hidetsugu IRIE Tsutomu YOSHINAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/12/01 Vol. E96-D No. 12 pp. 2545-2554 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Keyword: Network-on-Chip, high-bandwidth and low power network, optical interconnect, wavelength allocation,
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A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/04/01 Vol. E92-D No. 4 pp. 575-583 Type of Manuscript: PAPER Category: VLSI Systems Keyword: network-on-chip, FPGA, customize, router,
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A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1914-1922 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable System and Applications Keyword: Networks-on-Chip, FPGA, router, port combination,
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Architectural Design of Next-Generation Science Information Network Shigeo URUSHIDANI Shunji ABE Kensuke FUKUDA Jun MATSUKATA Yusheng JI Michihiro KOIBUCHI Shigeki YAMADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2007/05/01 Vol. E90-B No. 5 pp. 1061-1070 Type of Manuscript: Special Section PAPER (Special Section on Advanced Transfer Technologies for the Next Generation Network) Category: Keyword: hybrid network, multi-layer network, bandwidth on demand, L1VPN, GFP, VCAT, LCAS, GMPLS, MPLS,
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MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing Michihiro KOIBUCHI Akiya JOURAKU Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/01/01 Vol. E88-D No. 1 pp. 109-118 Type of Manuscript: PAPER Category: Computer Systems Keyword: output selection function, adaptive routing, virtual channel, interconnection networks, massively parallel computers,
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