Matsuaki TERADA


A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications
Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Matsuaki TERADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1957-1963
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
EthernetVSRbackplaneskewFECFire codes
 Summary | Full Text:PDF

FOREWORD
Matsuaki TERADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/01/01
Vol. E89-D  No. 1  pp. 111-111
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF