Masayuki OHAYASHI


Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOSSRAM
Kenichi OHHATA Takeshi KUSUNOKI Hiroaki NAMBU Kazuo KANETANI Toru MASUDA Masayuki OHAYASHI Satomi HAMAMOTO Kunihiko YAMAGUCHI Youji IDEI Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3  pp. 415-423
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
redundancyECL-CMOS SRAMSRAM with logic gateBiCMOS
 Summary | Full Text:PDF(892.2KB)

A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM
Hiroaki NAMBU Kazuo KANETANI Youji IDEI Toru MASUDA Keiichi HIGETA Masayuki OHAYASHI Masami USAMI Kunihiko YAMAGUCHI Toshiyuki KIKUCHI Takahide IKEDA Kenichi OHHATA Takeshi KUSUNOKI Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 739-747
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
 Summary | Full Text:PDF(793.7KB)