Masayoshi YOSHIMURA

A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT
Masayoshi YOSHIMURA Yoshiyasu TAKAHASHI Hiroshi YAMAZAKI Toshinori HOSOKAWA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2824-2833
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
transition faults, correlation, capture power reduction, X-filling, SAT, 
 Summary | Full Text:PDF(1.8MB)
A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution
Hiroshi YAMAZAKI Motohiro WAKAZONO Toshinori HOSOKAWA Masayoshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1994-2002
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
X-bit, don't care identification, X-bit distribution, test compaction, 
 Summary | Full Text:PDF(1.4MB)
Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time
Toshinori HOSOKAWA Masayoshi YOSHIMURA Mitsuyasu OHTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2722-2730
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
DFT strategies, full scan design methods, partial scan design methods, test point insertions, test application time, 
 Summary | Full Text:PDF(1.3MB)