Masayasu FUKUNAGA

On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis
Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1671-1677
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
path delay fault, untestable path, potentially testable path, fault efficiency, 
 Summary | Full Text:PDF
Evaluation of Delay Testing Based on Path Selection
Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA Shinichi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3208-3210
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
delay testing, path delay fault, path selection, untestable path, 
 Summary | Full Text:PDF