Masaya YOSHIKAWA

Security Evaluation of RG-DTM PUF Using Machine Learning Attacks
Mitsuru SHIOZAKI Kousuke OGAWA Kota FURUHASHI Takahiko MURAYAMA Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/01/01
Vol. E97-A  No. 1  pp. 275-283
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Hardware Based Security
Keyword: 
physical unclonable function (PUF), arbiter-PUF, XOR arbiter-PUF, RG-DTM PUF, machine learning attack, support vector machine (SVM), logistic regression (LR), 
 Summary | Full Text:PDF
Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System
Ryohei HORI Taisuke UEOKA Taku OTANI Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2182-2190
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
via programmable logic device, structured ASIC, exclusive-OR, middle-volume production, 
 Summary | Full Text:PDF
Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation
Ryohei HORI Tatsuya KITAMORI Taisuke UEOKA Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/09/01
Vol. E95-A  No. 9  pp. 1518-1528
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
via programmable logic device, structured ASIC, middle volume production, 
 Summary | Full Text:PDF
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications
Mitsuru SHIOZAKI Kota FURUHASHI Takahiko MURAYAMA Akitaka FUKUSHIMA Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 468-477
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Physical Unclonable Function (PUF), Arbiter-PUF, High Uniqueness, Responses Generation according to the Delay-Time Measurement (RG-DTM) scheme, 
 Summary | Full Text:PDF
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing
Akihiro NAKAMURA Masahide KAWARASAKI Kouta ISHIBASHI Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 509-516
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
via-programmable logic, electron-beam direct writing, low volume production, exclusive OR, structured ASIC, look-up table, 
 Summary | Full Text:PDF