IEICE Trans

Masaya MIYAHARA

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector Zule XU Anugerah FIRDAUZI Masaya MIYAHARA Kenichi OKADA Akira MATSUZAWA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 520-529 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: type-I, digital phase-locked loop, ring-based PLL,
	Summary \| Full Text:PDF(1.7MB)

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells Tohru KANEKO Yuya KIMURA Masaya MIYAHARA Akira MATSUZAWA
Publication: Publication Date: 2018/04/01 Vol. E101-C No. 4 pp. 197-205 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: delta sigma modulator, CMOS, high linearity,
	Summary \| Full Text:PDF(1.9MB)

A 7GS/s Complete-DDFS-Solution in 65nm CMOS Abdel MARTINEZ ALONSO Masaya MIYAHARA Akira MATSUZAWA
Publication: Publication Date: 2018/04/01 Vol. E101-C No. 4 pp. 206-217 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: complete-DDFS-solution, high-speed DDFS, CMOS, RDAC, RSTC-DEM, rail-to-rail operation, two-times interleaved,
	Summary \| Full Text:PDF(4.6MB)

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator Anugerah FIRDAUZI Zule XU Masaya MIYAHARA Akira MATSUZAWA
Publication: Publication Date: 2017/06/01 Vol. E100-C No. 6 pp. 548-559 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: charge-pump, delta-sigma, SAR ADC, time-to-digital converter,
	Summary \| Full Text:PDF(2.3MB)

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input Tohru KANEKO Yuya KIMURA Masaya MIYAHARA Akira MATSUZAWA
Publication: Publication Date: 2017/06/01 Vol. E100-C No. 6 pp. 539-547 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: current amplifier, CMOS, complementary input, wide bandwidth, low pass filter,
	Summary \| Full Text:PDF(2.2MB)

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell Mitsutoshi SUGAWARA Kenji MORI Zule XU Masaya MIYAHARA Kenichi OKADA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2435-2443 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: analog synthesis, RDAC, slice-based layout, SKILL language,
	Summary \| Full Text:PDF(2.2MB)

A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2^nd-Order Noise Shaping in 65nm CMOS Technology Yu HOU Zhijie CHEN Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2473-2482 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: Op-amp free, SAR, VCO, hybrid, 1-1 MASH ADC,
	Summary \| Full Text:PDF(2MB)

A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture Abdel MARTINEZ ALONSO Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/10/01 Vol. E99-C No. 10 pp. 1200-1210 Type of Manuscript: Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology) Category: Keyword: Direct Digital Frequency Synthesizer, Complementary Dual-Phase Latch-Based sequencing method, data sampling rate, CMOS,
	Summary \| Full Text:PDF(2MB)

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC Zhijie CHEN Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 pp. 963-973 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: fully passive noise shaping, charge-redistribution, SAR ADC, noise transfer function, zeros, poles,
	Summary \| Full Text:PDF(2.7MB)

Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC Zhijie CHEN Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 pp. 623-631 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: fully passive, SAR ADC, 1st order noise shaping, 2nd order noise shaping, charge-redistribution, noise transfer function,
	Summary \| Full Text:PDF(663.8KB)

Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques Lilan YU Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 pp. 641-650 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: high linearity, open-loop amplifier, nonlinearity cancellation, gain adapting,
	Summary \| Full Text:PDF(1.6MB)

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency Tohru KANEKO Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/04/01 Vol. E98-C No. 4 pp. 315-321 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology) Category: Keyword: Op-Amp, CMOS, Complementary Input, Gain Enhancement,
	Summary \| Full Text:PDF(618.8KB)

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology Yu HOU Takamoto WATANABE Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/02/01 Vol. E98-A No. 2 pp. 466-475 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: all-digital, reconfigurable resolution, TAD, low-voltage, sensor interface,
	Summary \| Full Text:PDF(2.6MB)

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC Zule XU Seungjong LEE Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/02/01 Vol. E98-A No. 2 pp. 476-484 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: ADPLL, charge pump, SAR-ADC, sub-picosecond resolution, TDC, time-to-charge conversion,
	Summary \| Full Text:PDF(1.6MB)

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique James LIN Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2400-2410 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: clock-scalable, common-mode voltage detection, dynamic amplifier, ultra-low-voltage, wide signal swing,
	Summary \| Full Text:PDF(2.4MB)

Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator Jeonghoon HAN Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 316-324 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: Injection-lock, ring oscillator, lock range, PLL,
	Summary \| Full Text:PDF(2.8MB)

A 7-bit 1-GS/s Flash ADC with Background Calibration Sanroku TSUKAMOTO Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 pp. 298-307 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: background calibration, ADC, offset cancel, interpolation,
	Summary \| Full Text:PDF(1.9MB)

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier Hyunui LEE Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2508-2515 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: analog-to-digital converter, interpolated pipeline topology, amplifier, body voltage control technique,
	Summary \| Full Text:PDF(2.1MB)

A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells Masao TAKAYAMA Shiro DOSHO Noriaki TAKEDA Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 813-819 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: time-domain architecture, time-to-digital converter, interleaving, successive approximation,
	Summary \| Full Text:PDF(2.6MB)

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers Hyunui LEE Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 838-849 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: analog-to-digital converter, pipeline topology, interpolation, ADC performance optimization,
	Summary \| Full Text:PDF(2.6MB)

A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs Fei LI Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 903-911 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: low-noise, high-dynamic, analog circuit, charge-sensitive amplifier, pixel readout LSI, particle detector,
	Summary \| Full Text:PDF(1008.3KB)

Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs Fei LI Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 568-576 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: analog circuit, particle detector, pixel readout LSI, Qpix, noise, gain, ADC, offset calibration,
	Summary \| Full Text:PDF(1.2MB)

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation Hyunui LEE Yusuke ASADA Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/02/01 Vol. E96-A No. 2 pp. 422-433 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog-to-digital converter (ADC), Capacitor DAC (CDAC), gate-weighted interpolation, digital offset calibration,
	Summary \| Full Text:PDF(2.9MB)

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching Hong Phuc NINH Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/06/01 Vol. E95-C No. 6 pp. 1017-1025 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: delta-sigma modulator, dynamic element matching, glitch energy, mismatch,
	Summary \| Full Text:PDF(1.8MB)

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator Daehwa PAIK Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/02/01 Vol. E95-A No. 2 pp. 456-470 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: dynamic amplifier, dynamic comparator, load capacitance, bypass current, calibration, and PVT variation,
	Summary \| Full Text:PDF(3.2MB)

An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques Daehwa PAIK Yusuke ASADA Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/02/01 Vol. E93-A No. 2 pp. 402-414 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog-to-digital converter, cyclic background calibration, self-calibration, interpolation,
	Summary \| Full Text:PDF(1.1MB)

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 pp. 469-475 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog to digital converter, pipeline operation, switched capacitor amplifier, low voltage operation, overdrive voltage,
	Summary \| Full Text:PDF(585.4KB)

The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time Masaya MIYAHARA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1165-1171 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: analog to digital converter, pipeline operation, switched capacitor amplifier, on resistance,
	Summary \| Full Text:PDF(589.8KB)