Masato MOTOMURA


FPGA-Based Annealing Processor with Time-Division Multiplexing
Kasho YAMAMOTO Masayuki IKEBE Tetsuya ASAI Masato MOTOMURA Shinya TAKAMAEDA-YAMAZAKI 
Publication:   
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2295-2305
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
ising modelannealing processorsimulated annealing
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Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
Kota ANDO Kodai UEYOSHI Yuka OBA Kazutoshi HIROSE Ryota UEMATSU Takumi KUDO Masayuki IKEBE Tetsuya ASAI Shinya TAKAMAEDA-YAMAZAKI Masato MOTOMURA 
Publication:   
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2341-2353
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
neural networkditheringerror diffusionFPGAhardware-oriented neural network algorithm
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FOREWORD
Masato MOTOMURA 
Publication:   
Publication Date: 2019/05/01
Vol. E102-D  No. 5  pp. 1002-1002
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
Li-Chung HSU Masato MOTOMURA Yasuhiro TAKE Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4  pp. 288-297
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
TCIThruChip3-D FPGATSVFPGATPRVPR
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A Hierarchical Cost Estimation Technique for High Level Synthesis
Mahmoud MERIBOUT Masato MOTOMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2  pp. 444-461
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high level synthesishardware cost estimationmultiplexer-based architecturebus-based architectureschedulingallocationpartitioning
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Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM
Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 759-767
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
integration of DRAM and logicembedded DRAMlow powerhigh memory bandwidth
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Cache-Processor Coupling: A Fast and Wide On-Chip Data Cache Design
Masato MOTOMURA Toshiaki INOUE Hachiro YAMADA Akihiko KONAGAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 623-630
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
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