Masato IWABUCHI


A 1.5-ns Cycle-Time 18-kb Pseudo-Dual-Port RAM with 9K Logic Gates
Masato IWABUCHI Masami USAMI Masamori KASHIYAMA Takashi OOMORI Shigeharu MURATA Toshiro HIRAMOTO Takashi HASHIMOTO Yasuhiro NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 749-755
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
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