Masaru UESUGI


A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture
Satoru TANOI Tetsuya TANABE Kazuhiko TAKAHASHI Sanpei MIYAMOTO Masaru UESUGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 898-904
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Logic
Keyword: 
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