Masaru OYA

Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning
Masaru OYA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2308-2319
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware Trojans, gate-level netlist, steady state, signal transition, logic test, 
 Summary | Full Text:PDF
Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching
Masaru OYA Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2335-2347
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware Trojans, gate-level netlist, a quantitative criterion, pattern matching, design phase, 
 Summary | Full Text:PDF
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists
Masaru OYA Youhua SHI Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Satoshi GOTO Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2537-2546
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
hardware Trojans, golden-IC free, classification, identification, gate-level netlist, 
 Summary | Full Text:PDF